RocketPuppy
commented
5 years ago Hi there! Thanks for your interest! First, apologies for the inactivity on this. This was originally a university project and when I finished real life things have gotten in the way of making any real progress.
Now, the inspiration. Ultimately it comes back to the John Backus Turing Award lecture "Can Programming be Liberated from the von Neumann Style?" (pdf). We've been stuck with fundamentally the same (with many major improvements) processing architecture for decades. Now we're hitting performance walls and the current trend is towards more parallelization and not faster processors. This project kind of took that idea and ran with it.
At it's core this is an implementation of parallel combinator graph reduction, with a specific slant towards being implemented in hardware. My overall vision for this is of many small, cheap processing units that can self-aggregate into a processing "mesh". Each unit can perform some reductions on a segment of a graph and the resulting reduced form is the program "result" (which may be another program!). In that way you end up with a massively parallel computing fabric.
There is prior work in this field, though most of it is from the 70s and 80s. GRIP was one such hardware implementation. See Simon Peyton-Jones other publications on that site for more applications and experiments conducted onit. Recently the Reduceron was another hardware implementation. Most recently what I've been keeping an eye on is the Formality language, which isn't (as far as I'm aware) aimed at hardware implementation but is aimed at optimal beta reduction.
emdash
I stumbled on this while reading Reddit posts about LLVM. This seems cool, but I am just wondering what the inspiration for all this was, and if you had any thoughts on what it might be good for. I have only a vague idea about Combinatory logic, but I am always interested in novel architectures.