search

CommonEvaluationPlatform / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
BSD 3-Clause "New" or "Revised" License
20 stars 6 forks source link

Cannot compile the chipyard #28

Closed jordankrim closed 4 months ago

jordankrim commented 5 months ago

I am using V4.5 of the CEP and I cannot compile the chipyard as per the instructions:

make -f Makefile.chipyard

Running with RISCV = cep_v_4_4_test_new_rtl/CEP/.conda-env/riscv-tools Running with SUB_PROJECT = cep_cosim

common.mk:81: generators/nvdla/nvdla.mk: No such file or directory make: *** No rule to make target 'generators/nvdla/nvdla.mk'. Stop.

Not only is nvdla directory empty, but there are no files in directories ibex and cva6. (whereas in my V4.4 sandbox there are files). Also, I have a V4.4 sandbox and I see a directory called: generators/mitll-blocks/target This directory is missing from my V4.5 sandbox and I am wondering if the "target" dir is be generated by the chipyard make or is it supposed to be there beforehand?

bchetwynd commented 5 months ago

Looks like your chipyard did not properly initialize when you ran `build-setup.sh'. Part of that process is ensuring the submodules are properly initialized.

jordankrim commented 5 months ago

You are correct. I fixed the issue, but I need to figure out how to dump waveforms when running for example a bareMetal test to debug some failures I am having vs. the v4.4 CEP.

jordankrim commented 5 months ago

I am trying to build a Verilated simulation model. When I try to do: make SUB_PROJECT=cep_verilator I get this:

Error: Option --top-module failed when given 'chipyard.harness.'. chipyard.harness. Try --help for more information.

jordankrim commented 5 months ago

Has compilation with Verilator been done with version 4.5 of the CEP. I just got my "old" v4.4 working, but much has changed in the Makefiles and I am getting that -top-module failure when trying to compile with Verilator on v4.5 now. Is there a different way to run the Makefiles now in this version. I just ran: make SUB_PROJECT=cep_verilator

bchetwynd commented 5 months ago

Unfortunately, I get the same result with v4.5. I'm just about to release v4.6 and will ensure cep_verilator builds correctly.

jordankrim commented 5 months ago

I was able to hack a Makefile (to set --top-module correctly maybe?) and I got further, unfortunately when I tried to run the make SUB_PROJECT=cep_verilator it got further but still gets: verilator --cc --exe --trace -CFLAGS " -O3 -std=c++17 -I/mnt/data/projects/project/jkrim/chipname/.conda-env/riscv-tools/include -I/mnt/data/projects/project/jkrim/chipname/tools/DRAMSim2 -I/mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral -DVERILATOR -include /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig.plusArgs" -LDFLAGS " -L/mnt/data/projects/project/jkrim/chipname/.conda-env/riscv-tools/lib -Wl,-rpath,/mnt/data/projects/project/jkrim/chipname/.conda-env/riscv-tools/lib -L/mnt/data/projects/project/jkrim/chipname/sims/verilator -L/mnt/data/projects/project/jkrim/chipname/tools/DRAMSim2 -lriscv -lfesvr -ldramsim " --threads 1 --threads-dpi all -O3 --x-assign fast --x-initial fast --output-split 10000 --output-split-cfuncs 100 --assert -Wno-fatal --timescale 1ns/1ps --max-num-width 1048576 +define+CLOCK_PERIOD=1.0 +define+RESET_DELAY=777.7 +define+PRINTF_COND=TestDriver.printf_cond +define+STOP_COND=!TestDriver.reset +define+MODEL=TestHarness +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN +define+VERILATOR --top-module TestHarness --vpi -f /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/sim_files.common.f -o /mnt/data/projects/project/jkrim/chipname/sims/verilator/simulator-chipyard.harness-CEPVerilatorRocketConfig -Mdir /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig -CFLAGS "-include /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/VTestHarness.h" %Warning-REDEFMACRO: Redefining existing define: 'VERILATOR', with different value: '' ... Location of previous definition, with value: '1' ... For warning description see https://verilator.org/warn/REDEFMACRO?v=5.008 ... Use "/ verilator lint_off REDEFMACRO /" and lint_on around source to disable this message. %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_assert.sv:74:11: Cannot find include file: prim_assert_dummy_macros.svh 74 | include "prim_assert_dummy_macros.svh" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_assert.sv:74:11: This may be because there's no search path specified with -I<dir>. 74 |include "prim_assert_dummy_macros.svh" | ^~~~~~~~~~ ... Looked in: prim_assert_dummy_macros.svh prim_assert_dummy_macros.svh.v prim_assert_dummy_macros.svh.sv /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/prim_assert_dummy_macros.svh /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/prim_assert_dummy_macros.svh.v /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/prim_assert_dummy_macros.svh.sv %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:30:10: Cannot find include file: prim_assert.sv 30 | include "prim_assert.sv" | ^~~~~~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:100:3: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 100 |ASSERT_INIT(srot_slaveTlSzw, top_pkg::TL_SZW >= SLAVE_TL_SZW) | ^~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:100:15: syntax error, unexpected '(' 100 | ASSERT_INIT(srot_slaveTlSzw, top_pkg::TL_SZW >= SLAVE_TL_SZW) | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:101:3: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 101 |ASSERT_INIT(srot_slaveTlAiw, top_pkg::TL_AIW >= SLAVE_TL_AIW) | ^~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:102:3: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 102 | ASSERT_INIT(srot_slaveTlAw, top_pkg::TL_AW >= SLAVE_TL_AW) | ^~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:103:3: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 103 |ASSERT_INIT(srot_slaveTlDbw, top_pkg::TL_DBW == SLAVE_TL_DBW) | ^~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:104:3: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 104 | ASSERT_INIT(srot_slaveTlDw, top_pkg::TL_DW == SLAVE_TL_DW) | ^~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:110:24: syntax error, unexpected '[', expecting IDENTIFIER or randomize 110 | slave_tl_h2d.a_size[SLAVE_TL_SZW-1:0] = slave_a_size; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:111:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 111 | slave_tl_h2d.a_source = '0; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:112:26: syntax error, unexpected '[', expecting IDENTIFIER or randomize 112 | slave_tl_h2d.a_source[SLAVE_TL_AIW-1:0] = slave_a_source; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:113:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 113 | slave_tl_h2d.a_address = '0; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:114:27: syntax error, unexpected '[', expecting IDENTIFIER or randomize 114 | slave_tl_h2d.a_address[SLAVE_TL_AW-1:0] = slave_a_address; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:120:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 120 | slave_tl_h2d.a_valid = slave_a_valid; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:121:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 121 | slave_tl_h2d.a_opcode = ( slave_a_opcode == 3'h0) ? PutFullData : | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:125:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 125 | slave_tl_h2d.a_param = slave_a_param; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:126:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 126 | slave_tl_h2d.a_mask = slave_a_mask; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:127:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 127 | slave_tl_h2d.a_data = slave_a_data; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:128:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 128 | slave_tl_h2d.a_user = tl_a_user_t'('0); | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/llki_pp_wrapper.sv:129:49: syntax error, unexpected '=', expecting IDENTIFIER or randomize 129 | slave_tl_h2d.d_ready = slave_d_ready; | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:8:10: Cannot find include file: prim_assert.sv 8 |include "prim_assert.sv" | ^~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:36:5: Define or directive not defined: 'ASSERT_INIT' : ... Suggested alternative: 'ASSERT_IF' 36 | ASSERT_INIT(paramCheckPass, Pass == 1) | ^~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:36:17: syntax error, unexpected '(' 36 |ASSERT_INIT(paramCheckPass, Pass == 1) | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:149:5: Define or directive not defined: 'ASSERT' : ... Suggested alternative: 'ASSERT_IF' 149 | ASSERT(depthShallNotExceedParamDepth, !empty |-> depth_o <= DepthW'(Depth)) | ^~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:149:12: syntax error, unexpected '(' 149 |ASSERT(depthShallNotExceedParamDepth, !empty |-> depth_o <= DepthW'(Depth)) | ^ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:157:3: Define or directive not defined: 'ASSERT' : ... Suggested alternative: 'ASSERT_IF' 157 | ASSERT(DataKnown_A, rvalid_o |-> !$isunknown(rdata_o)) | ^~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:158:3: Define or directive not defined: 'ASSERT_KNOWN' : ... Suggested alternative: 'ASSERT_KNOWN_IF' 158 |ASSERT_KNOWN(DepthKnown_A, depth_o) | ^~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:159:3: Define or directive not defined: 'ASSERT_KNOWN' : ... Suggested alternative: 'ASSERT_KNOWN_IF' 159 | ASSERT_KNOWN(RvalidKnown_A, rvalid_o) | ^~~~~~~~~~~~~ %Error: /mnt/data/projects/project/jkrim/chipname/sims/verilator/generated-src/chipyard.harness.TestHarness.CEPVerilatorRocketConfig/gen-collateral/prim_fifo_sync.sv:160:3: Define or directive not defined: 'ASSERT_KNOWN' : ... Suggested alternative: 'ASSERT_KNOWN_IF' 160 |ASSERT_KNOWN(WreadyKnown_A, wready_o) | ^~~~~ %Error: Cannot continue

bchetwynd commented 5 months ago

Jordan, it comes down to that the include directories for verilator are not being created properly, and thus it can't find the file. I'd recommend waiting util I release v4.6, which should be later today.

jordankrim commented 5 months ago

Brendon, it also appears that for some reason the DFT (on CPU 2) and IDFT (on CPU 3) on the bareMetal test macro4Mix are timing out using Xcelium whereas on v4.4 they ran fine and the testcase passed. They also passed with Verilator on v4.4.

bchetwynd commented 5 months ago

Jordan, thanks for the note. I believe that is still the case for v4.6. If you would be willing to file a separate issue, that would be appreciated.

jordankrim commented 5 months ago

One other thing. The fullBoot bareMetal test with Xcelium is running both on v4.4 and v4.5 right now and it is taking a really long time. Seems like the Verilator fullBoot on v4.4 ran fast and passed. I don't know if I am just impatient, or it should take a long time to run. Maybe it will timeout eventually or finish pass/fail?

bchetwynd commented 5 months ago

In short, fullBoot won't work with the SUB_PROJECT=cep_verilator target. It only works with SUB_PROJECT=cep_cosim since it relies on a custom testbench that is not part of chipyard.

jordankrim commented 4 months ago

It worked on v4.5 with Xcelium. Ran to about 5ms. (Looks like v4.4 hung but maybe a don't care?). Please let me know when v4.5 is released. Thanks,

bchetwynd commented 4 months ago

v4.6 was released a few hours ago.

jordankrim commented 4 months ago

Is there any way to "hack" the Makefiles of v4.5 to get Verilator to work? I may have to wait a long time for v4.6 to be ready for me to use and so I'm trying to use what I have for now.

bchetwynd commented 4 months ago

I'm sure there is a way to hack v4.5, but I don't currently have the bandwidth to track it down.

jordankrim commented 4 months ago

If I do a clone from the repo, will that be 4.6?

bchetwynd commented 4 months ago

A clone of the current state of the repo will give you v4.6. You can also checkout the explicit v4.6 tag to be sure.

jordankrim commented 4 months ago

And does (from sims/verilator): make SUB_PROJECT=cep_verilator work? Because in the variables.mk there is this which makes no sense since the var VLOG_MODEL is overwritten:

ifeq ($(SUB_PROJECT),cep_verilator) SBT_PROJECT ?= chipyard VLOG_MODEL ?= $(MODEL) VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= chipyard.harness CONFIG ?= CEPVerilatorRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver TOP ?= ChipTop SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py SORT_FILE := $(base_dir)/cep_sort.f BOOTROM_SRC_DIR := $(base_dir)/generators/testchipip/src/main/resources/testchipip/bootrom endif

bchetwynd commented 4 months ago

Unfortunately, there is a mistake in variables.mk. Here is the correct SUB_PROJECT definition for cep_verilator:

ifeq ($(SUB_PROJECT),cep_verilator) SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= $(MODEL) MODEL_PACKAGE ?= chipyard.harness CONFIG ?= CEPVerilatorRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver TOP ?= ChipTop SORT_SCRIPT := $(base_dir)/scripts/sort-blackbox.py SORT_FILE := $(base_dir)/cep_sort.f BOOTROM_SRC_DIR := $(base_dir)/generators/testchipip/src/main/resources/testchipip/bootrom endif

Rhere still seems to be some issues with the verilator build that it is not pulling in one of the verilog files that defines assertions. I'd suggest filing a separate issue and I will try to get to it soon.

jordankrim commented 4 months ago

Yes. I discovered that. So, I was able to compile the chipyard with Verilator it seems. I was also able to create the .elf files and others for the aesMacro bareMetal test but when I try to run the command, I get a cryptic error:

./simulator-chipyard.harness-CEPVerilatorRocketConfig ../../sims/cep_cosim/testSuites/bareMetalTests/aesMacro/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/aesMacro/riscv_wrapper.hex +loadmem_addr=80000000 simulator-chipyard.harness-CEPVerilatorRocketConfig: ../fesvr/elfloader.cc:37: std::map<std::__cxx11::basic_string, long unsigned int> load_elf(const char, memif_t, reg_t, unsigned int): Assertion `(((eh64).e_ident[0] == 0x7f && (eh64).e_ident[1] == 'E' && (eh64).e_ident[2] == 'L' && (eh64).e_ident[3] == 'F') && (eh64).e_ident[4] == 1) || (((eh64).e_ident[0] == 0x7f && (eh64).e_ident[1] == 'E' && (eh64).e_ident[2] == 'L' && (eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 2)' failed.

Is the command I have given correct and if so any idea what this failure is? Here is a hex dump first line of the riscv_wrapper.elf:

00000000: 7f45 4c46 0201 0100 0000 0000 0000 0000 .ELF............

That seems to agree with the checker above yet it fails.

bchetwynd commented 4 months ago

My only immediate thought is to ensure you are compiling the executable (aesMacro/riscv_wrapper.hex) within the same Conda environment you compiled cep_verilator. Other than that, I would need to spend some time exploring

jordankrim commented 4 months ago

I am trying to debug it, but I need to add "printf" statements to the elfloader.cc file. How do I re-compile it and then will I actually get prints out for debugging?

Followup: I went to toolchains/riscv-tools/riscv-isa-sim/build and did a make. It appears that elfloader.o is changed, however, I have added 3 lines of prints above the failing line 37 reported (see above) but when I run the test again it still reports the failure as on line 37. So it looks like the elfloader.cc that I modified is not being used. I redid the: make SUB_PROJECT=cep_verilator also and rebuilt all the baremetal test .elf files, but nothing seems to print and the line 37 is still being reported as the error, so how do I successfully compile and utilize a change elfloader.cc file?

bchetwynd commented 4 months ago

Jordan, these questions are not related to the original issue you had. Please either file a new issue or email me directly.