The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
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VERILATOR: Baremetal tests on Verilator are only single-core #3
The entry point for the bare metal (riscv_wrapper) executables was changed for verilator since it excepts a "main" in the elf.
There is some initialization (assembly???) logic that is not immediately visible.... and the bootrom is not used.
Open question: How to run multi-core tests in verilator. Do I simply need to fork threads in main?