Contiguous Memory incorrectly addressed in memory interconnect

[cospan]

The memory interconnect bus presents a contiguous absolute memory interface across an arbitrary number of memory slaves:

For example if the ibuilder configuration file specifies a memory bus as the first device on the memory bus and then an SDRAM for the second device on the memory bus the memory interconnect will only present one contiguous abstraction of memory, visually it would look like this:

Currently the memory interconnect does not modify any of the addresses that are relayed from the master to the slave. This is incorrect.

If (from the above example) the BRAM size is 0x100 and the SDRAM size is 0x1000.

-If the user attempted to read/write from/to address 0x00 - 0xFF the BRAM would be accessed -If the user attempted to read/write from/to address 0x0100 to 0x0FFF the SDRAM would be accessed but the address of that access would start at 0x100 not 0x00 (relative to SDRAM)

-If the user attempted to read/write from/to address 0x1000 to address 0x10FF then there would be an error as this would be out of range from the SDRAM

The fix will require a change in the memory interconnect generation script: /nysa/ibuilder/lib/gen_scripts/gen_mem_interconnect.py where the o_wbs_adr

Try this out: The memory interconnect should the offset to the memory address

[cospan]

Finally got around to this, memory is not layed out in a contiguous fashion