Closed cospan closed 8 years ago
When observing the logic analyzer signals in GTKWave the upper bits (31 - 29) are incorrectly represented in the view.
This is most likely due to a mistake in the host software
nysa/host/logic_analyzer
Specifically where the logic analyzer assembles the signals into the vcd file format.
I believe this might be related to the desire to add a fake clock to the logic analyzer signals so instead of 32 signals being written there is 33.
When observing the logic analyzer signals in GTKWave the upper bits (31 - 29) are incorrectly represented in the view.
This is most likely due to a mistake in the host software
nysa/host/logic_analyzer
Specifically where the logic analyzer assembles the signals into the vcd file format.
I believe this might be related to the desire to add a fake clock to the logic analyzer signals so instead of 32 signals being written there is 33.