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CospanDesign / nysa

FPGA Development toolset
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valid verilog module syntax is not recognized #6

Open cospan opened 9 years ago

cospan commented 9 years ago

When building an FPGA image the tool analyzes verilog modules to determine if build depends on them,

A module can be declared with the beginning parenthesis on the first line:

module verilog_module (

or with the parenthesis on the second line

module verilog_module (

The system is not recognizing the second version

cospan commented 8 years ago

generate statements confuse the verilog parser