NOT A ISSUE! advising STM32L073RZ Nucleo working properly with swdcom

[techman-001]

Mecrisp-Stellaris RA 2.5.4 with M0 core for STM32L073RZ by Matthias Koch

I prepended the following Mecrisp-Stellaris startup code to terminal-m0.s and swapped .include "../common/catchflashpointers.s" and bl uart_init in the mecrisp-stellaris-stm32l073rz.s.

@@@@@@@@@@@@@@@@@@@@@@@@ @ Mecrisp-stellaris startup code @@@@@@@@@@@@@@@@@@@@@@@@ .equ GPIOA_BASE , 0x50000000 .equ GPIOA_MODER , GPIOA_BASE + 0x00 .equ GPIOA_OTYPER , GPIOA_BASE + 0x04 .equ GPIOA_OSPEEDR , GPIOA_BASE + 0x08 .equ GPIOA_PUPDR , GPIOA_BASE + 0x0C .equ GPIOA_IDR , GPIOA_BASE + 0x10 .equ GPIOA_ODR , GPIOA_BASE + 0x14 .equ GPIOA_BSRR , GPIOA_BASE + 0x18 .equ GPIOA_LCKR , GPIOA_BASE + 0x1C .equ GPIOA_AFRL , GPIOA_BASE + 0x20 .equ GPIOA_AFRH , GPIOA_BASE + 0x24 .equ GPIOA_BRR , GPIOA_BASE + 0x28

.equ RCC_BASE , 0x40021000 .equ RCC_CR , RCC_BASE + 0x00 .equ RCC_CFGR , RCC_BASE + 0x0C .equ RCC_IOPENR , RCC_BASE + 0x2C .equ RCC_AHBENR , RCC_BASE + 0x30 .equ RCC_APB2ENR , RCC_BASE + 0x34 .equ RCC_APB1ENR , RCC_BASE + 0x38

.equ PWR_BASE , 0x40007000 .equ PWR_CR , PWR_BASE + 0x00 .equ PWR_CSR , PWR_BASE + 0x04

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ Voltage reg and 16MHz clock setup @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ Switch internal voltage regulator to high-performance "Range 1" ldr r1, = PWR_CR ldr r0, = BIT11 str r0, [r1]

@ Select 16 MHz HSI clock instead of MSI which is boot default ldr r1, = RCC_CR movs r0, #1 @ HSI on str r0, [r1]

1:ldr r0, [r1] @ Check HSIRDY flag movs r2, #4 ands r0, r2 beq 1b

ldr r1, = RCC_CFGR movs r0, #1 @ HSI as system clock source str r0, [r1]

@ Turn on the clocks for all GPIOs. ldr r1, = RCC_IOPENR ldr r0, = BIT0 + BIT1 + BIT2 + BIT3 + BIT7 @ IOPAEN IOPBEN IOPCEN IOPDEN IOPHEN str r0, [r1]

[Crest]

Thank you for testing swdcom on a STM32L073RZ chip.