MOSFET Board

[SergiuPetrut]

Try to make a prototype board of the MOSFET design before we order the PCBs

[Zhguye]

I'll write a long explanation text so when the mistake in the PCB happens it is easier to notice what I missed.

MOSFET (FDS6898AZ) Voltage value needs to be between +12V & +1.5V ( Gate-Source Voltage & Gate Threshold Voltage). No drain voltage because drains are connected together and cells are connected to the source pins. Since the MOSFET we use is an N-type, we need a pull-down resistor from the gate. (A P-type would use a pull-up resistor).

There are internal capacitors in the MOSFET that are important for the switching operations, like speed. HOWEVER, NOTE THE VALUES ARE THE CAPACITANCE OF AREAS AND NOT THE CAPACITANCE OF SPECIFIC CAPACITORS. My Japanese brethren have given a detailed explanation as usual https://toshiba.semicon-storage.com/info/application_note_en_20230209_AKX00063.pdf?did=13415

I'm not sure if these internal capacitors are the reason the MOSFET behaves like a capacitor, however I think our MOSFET behaves like a voltage-controlled variable capacitor.

Time values and other stuff are on the datasheet (useful stuff)? The higher the gate charge, the higher the dissipation losses. :( Drain voltages also affect switching :( Drain–Source On–Resistance should as small as possible The switching time of a transistor is inversely proportional to the amount of current used to charge the gate.

MOSFET Gate Drivers exist. Their purpose is to safeguard the circuit from overcurrent (I think). I would say these aren't needed for our project because we aren't switching the MOSFET fast and often enough.

and I still think we need resistors, preferably 10k, from the gate to the source of every MOSFET. The reason being ESD. I don't think any group has yet to test a MOSFET so this problem has yet to occur.

This circuit layout is overthought if anything, I am not sure about all those pulldown resistors. I'll try to make a second circuit just to make sure.

[Zhguye]

This is my idea for the switching, pull-down for charge and pull-up for discharge

[Zhguye]

I think this is the proper circuit style. C2/load at the bottom would be the negative polarity of the charger.

The logic of the original bms:

From this picture you can see that all the source pins have that copper wire that go to the P&B plates.

[TruthSeekerX]

[TruthSeekerX]

Theoretical gate resistor could be 132R for 25mA Absolute Maximum Current of STM32L152RE IO pins. But we could use a bigger one, no need to go to the edge. For example 200ohm, would limit the current to 16.5mA

[TruthSeekerX]

Pull down resister is good.