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DECAfpga / SNES

SNES core
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Not a issue, just a question about chips #1

Closed Alirio926 closed 2 years ago

Alirio926 commented 2 years ago

Hello! I have a question about CX4 implementation, why has a 1MB sram for this chip? What is the use of this sram?

Thanks!!!

Sorry my lack of knowledge, i jumped into https://wiki.superfamicom.org/capcom-cx4-hitachi-hg51b169 and know now the chip does support to sram, but never is used.

However, where is found the prom.mif that is referenced inside prom.vhd?

somhi commented 2 years ago

Your welcome!! I just did the port to DECA FPGA but don't know very well the internal details of the core.

I can confirm you that this core is running fine only with SDRAM memory.

Sorry but I didn't find any of the two files referenced by you in my port.

Alirio926 commented 2 years ago

Thanks for the answer. Ill try run this modules, but iI have some question, and I will be grateful if you can answer. Is SYSCLKF_CE, SYSCLKFR_CE the falling and rising edge from what clk? What frequency? maybe 21.477MHZ What time u sdram resp a read?

I tried another CX4 code, and works, but some glitch on screen, i think it's because 70ns memory. https://github.com/srg320/FpgaSnes/tree/master/FPGA/chip/CX4 i want to try this repository, but need solve the need for SYSCLKx_CE.

somhi commented 2 years ago

Sorry don't know those details. You might ask that at the original repository. This is just a fork so no development has been made here.