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DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
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Output file was not written #4

Closed vidyamidhun closed 9 months ago

vidyamidhun commented 9 months ago

The entire project run without any simulation errors. The input and output locations are also given properly. But was unable to get the outcom.bmp file as output image.

DOUDIU commented 9 months ago

Here are two possible problems:

1.The default simulator is ModelSim. If you use Vivado as your simulator, change the macro definition at the beginning of the haze_removal_tb.sv file. 2.If you simulate for enough time, the 720p BMP files will be generated after 13ms. The higher the resolution, the more time it will take.

vidyamidhun commented 9 months ago

Thanks a lot. It worked. I have simulated the code for 13ms and was able to generate the output.