search

DSi-DV / rv64g-core

The RV64G Core is a 64-bit RISC-V compliant core designed in SystemVerilog. It includes the RV64IMAFD extensions, providing integer, multiplication/division, atomic, floating-point, and double-precision floating-point
MIT License
1 stars 0 forks source link

rv64g_instr_decoder_tb #18

Closed foez-ahmed closed 2 days ago

foez-ahmed commented 5 days ago

Testbench Needed

foez-ahmed commented 4 days ago

Properly discuss and collaborate with each other

foez-ahmed commented 2 days ago

New field has been introduced in the decoded_instr_t from f192880713b6d2a96904a17cf475f9686faa28cd commit. Please mind that during TB developments

  typedef struct packed {
    func_t       func;
    logic [5:0]  rd;
    logic [5:0]  rs1;
    logic [5:0]  rs2;
    logic [5:0]  rs3;
    logic [63:0] imm;
    logic [63:0] pc;
    logic        jump;
    logic [63:0] reg_req;
  } decoded_instr_t;
SubhanBihan commented 2 days ago

Bhai, what type of documentation should we follow for the instruction set? I could just search it up online but there's always a chance it might not be exactly the same protocol as you followed.

Also it'd be helpful if you could update and elaborate on the rv64g_inst_decoder (module) doc in README.

foez-ahmed commented 2 days ago

A few info have been added in the rv64g_instr_decoder rtl doc from commit ac9b95e987ad8add2c2bec09d5c8aecf29ce2f7c onwards

foez-ahmed commented 2 days ago

RTL no longer exist

foez-ahmed commented 2 days ago

Automation Auto closing this issue after file rename.