Closed kmanolop closed 2 years ago
@kmanolop am I correct in thinking the expected operation is to set the register to 1 and then back to 0 ?
Having tested this in the questa project simulation, I am fairly certain that toggling the register won't work for our use case. I think with the current firmware, the register needs to be set to 1 when the ADC packet actually hits the pedsub block for it to use that first sample as the median
thanks @aearle-su. Does this not work if the control register bit is held high until the next packet?
It does, so I just set it to write it high and it adjusted the pedestal for each wire when testing with the FixedADC_A pattern as that one has 500 and 900 pedestals I think
pedsub_adj isa signal used by the Pedestal Subtraction block to adjust the median value to that of the incoming ADC values. This operation takes place when the signal is set to '1'. DTP-controls should handle the register corresponding to that signal.
Changes made in the stream_processor.xmld addrtab are: