There have 2 lines. Data and Clock.
Every frame has 128 Clock Cycles.
Cycles 4 a 63 - Main CPU send information for Output
Cycles 68 a 127 - Main CPU Receive information of inputs.
The first Cycles 0 to 3 and 64 to 67 are sync singals. Status and Command
for Write or Read
ianles...@gmail.com, Sep 6, 2009
Who controls the clock? Is the clock bidirectional, or does the master always provide
the clock? It might work with the existing raw 2 wire library. The repeat read and
write commands make it easy to enter a bunch of bytes (0:59 to send 0, 59 times; r:59
to read 59 bytes).
Why is the physical layer? Is it simple +5volts/ground or is it some funky modulation
scheme?
Most importantly, do you have hardware to test it with? This sounds like a useful
protocol for techs, but I'd never be in a position to test it myself.
BrentBXR, Nov 22, 2011
0 1c th4t 15 s0o c0ol. I would imagine people working on elevators have specialized equipment todo so. I would never take my bus pirate to go hacking elevators. Not that the bus pirate shouldn't have every protocol it can fit. It just seems this would be on the rarely, if ever, used list. I doubt Ian or the DP guys could make time to implement it when other, more used, protocols are still pending.
co0l u5ag3 of num8er5 a5 13773r5 7h0, rather annoying really. :P
Although this was discussed many years ago now, it does not appear the questions have been answered, and I believe it could still be of interest for some people. At least, for me it is. So here is some information I have gathered so far.
On modern generations (gen2 for example), the bus is composed of 4 wires. L1 (for data), L2 (for clock), +30VDC and GND. It would make sense for the clock to be generated by the main controller. I would assume it is some kind of I2C.
As the bus runs for dozens of meters down the hoistway, special care should probably be taken when designing an adaptation circuit for the bus pirate since capacitance and pull-up resistor values will have an impact on achievable data rates.
I am importing this issue from the old google code repository, https://code.google.com/p/the-bus-pirate/issues/detail?id=37.
alvaro.e...@gmail.com, Sep 5, 2009
ianles...@gmail.com, Sep 6, 2009
BrentBXR, Nov 22, 2011
Although this was discussed many years ago now, it does not appear the questions have been answered, and I believe it could still be of interest for some people. At least, for me it is. So here is some information I have gathered so far.
On modern generations (gen2 for example), the bus is composed of 4 wires. L1 (for data), L2 (for clock), +30VDC and GND. It would make sense for the clock to be generated by the main controller. I would assume it is some kind of I2C.
As the bus runs for dozens of meters down the hoistway, special care should probably be taken when designing an adaptation circuit for the bus pirate since capacitance and pull-up resistor values will have an impact on achievable data rates.
Cheers.