search

David-Durst / aetherling

Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
MIT License
12 stars 1 forks source link

Dashes in generated verilog names #11

Closed adamdai closed 6 years ago

adamdai commented 6 years ago

Verilog generated by coreir for aetherling ReduceSequential module contains names with dashes, which cannot be interpreted by yosys.

Steps to reproduce:

  1. Clone the repo: https://github.com/adamdai/magmacam.git
  2. In the aetherling folder, run python reducehybrid.py
  3. Then run ./coreir_compile.sh reducehybrid IceStick
  4. The generated verilog can now be found in IceStick/build as reducehybrid.v. The variables with dashes are under the reduceSequential module (line 459, 488)

If you want to run the code

  1. In the IceStick folder, run ./bake
  2. Go to IceStick/build and run ./cat_verilog
  3. Now run make, which should give the following error 
    ERROR: Parser error in line reduce_test.v:813: syntax error, unexpected '-', expecting ',' or '=' or ';' or '['
make: *** [reduce_test.bin] Error 1
David-Durst commented 6 years ago

https://github.com/rdaly525/coreir/pull/590 fixes this. Feel free to use the branch at https://github.com/David-Durst/coreir/tree/fixAeConstNames until the pull request gets accepted.