CoreIR URem Not Being Generator For Verilator

[David-Durst]

When I run a test that requires an unsigned remainder module, I get the following error:

E               Exception: Running verilator cmd verilator -Wall -Wno-INCABSPATH -Wno-DECLFILENAME -Wno-fatal --cc STBankGenerator_no2_ni3_ii0_tEl1_hasCEFalse_hasResetFalse.v  --exe STBankGenerator_no2_ni3_ii0_tEl1_hasCEFalse_hasResetFalse_driver.cpp --top-module STBankGenerator_no2_ni3_ii0_tEl1_hasCEFalse_hasResetFalse failed: %Error: STBankGenerator_no2_ni3_ii0_tEl1_hasCEFalse_hasResetFalse.v:83: Can't resolve module reference: coreir_urem__width3

Note the issue Can't resolve module reference: coreir_urem__width3. The first line of the verilog produced by CoreIR says:

// Module `urem` defined externally

How do I link in urem?

[David-Durst]

Per @rdaly525 , it's standard for unsigned remainder to not be synthesizable. I'll need to implement it if I want it. See https://forums.xilinx.com/t5/Synthesis/Modulus-synthesizable-or-non-synthesizable/td-p/747493