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David-Durst / aetherling

Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
MIT License
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CoreIR Won't Compile Circuit That Simulates Correctly #24

Open David-Durst opened 5 years ago

David-Durst commented 5 years ago

This test runs correctly: https://github.com/David-Durst/aetherling/blob/52143b265a4fa76135c0975bf1cc4e6bf20b0c76/tests/test_rshift.py#L9-L32

The same test except using fault fails: https://github.com/David-Durst/aetherling/blob/52143b265a4fa76135c0975bf1cc4e6bf20b0c76/tests/test_rshift.py#L34-L61. It fails on the call the CoreIR compiler that generates verilog. The error message is below. @rdaly525 any thoughts? This looks like a bug in CoreIR.

python: /home/david/dev/coreir/src/ir/context.cpp:112: void CoreIR::Context::die(): Assertion `0' failed.
Fatal Python error: Aborted

Current thread 0x00007efbff6e1740 (most recent call first):
  File "/home/david/dev/pycoreir/coreir/module.py", line 135 in save_to_file
  File "/home/david/dev/magma/magma/compile.py", line 56 in __compile_to_coreir
  File "/home/david/dev/magma/magma/compile.py", line 136 in compile