It appears we are trading in hypotheticals.
ading in hypothetical.
In the 2020/7/17 meeting we went over this issue again. The consensus at the meeting was to stay with PoR, which might alter vl when SEW/LMUL ratio changes rather than set vill. The sentiment was that the debugging value was small, and there was some potential uses for the behavior.
Rereading Guy's comments above again, the register form of vsetvl case was not considered in TG discussion. Though that is a relatively rare form of the instruction., and in general won't benefit from static checking (e.g., for unsupported SEW).
We did discuss making the behavior in these cases "reserved", so we could redefine those cases in future to perform some useful alternative vl setting function, but this would not enable forward compatibility via emulation (neither would setting vill), so the decision was that a different encoding should be used when a different function is required. This makes me reconsider our PoR.
For a while, I've been trying to think of cases where a vsetvli x0,x0, with different SEW/LMUL would perform a useful function and I struggle with coming up with plausible use cases. One example I had thought of was when taking a vector of say bytes and wanting to cast these into vector of halfwords. The instruction could be used to change vl appropriately, though only in one direction and this only really works when vl=VLMAX initially, which we can accomplish more reliably using the rd!=x0, rs1=x0 variant.
More methodically, when new SEW'/LMUL' > existing SEW/LMUL, then vl might either stay the same or be clipped. I struggle to see the utility there for portable software.
When SEW'/LMUL'<SEW/LMUL then vl will be unchanged, but upper portions of vector register groups at SEW' will be inaccessible. There might be use there, but it seems a bit esoteric. While one could possibly use the lower portions of a vector register group to work with other vector register groups, the same effect would be had simply using a different LMUL to keep the upper portion undisturbed (and maybe set tail-undisturbed for fractional LMUL.
I am coming around to the idea the vsetvl{I} x0, x0 form should set vill if SEW/MUL ratio would change, leaving vl unchanged in all cases. This might also simplify hardware as there is no potential change in vl with this instruction.
It appears we are trading in hypotheticals. ading in hypothetical.