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DavidGriffith / minipro-import-test

An open source program for controlling the MiniPRO TL866xx series of chip programmers
GNU General Public License v3.0
3 stars 0 forks source link

Contribution for logic tester: Commodore 64 PLA #284

Open DavidGriffith opened 1 year ago

DavidGriffith commented 1 year ago

In GitLab by @f1ac0 on Mar 2, 2023, 14:38

Hi, This is not an issue.

The web page below shares how to test a Commodore 64 PLA using a TL866-II+ and Xgpro. http://www.breakintoprogram.co.uk/hardware/fixing-a-poorly-commodore-64-part-3

I believe it should also work a TL866 using minipro. I do not have a working chip to confirm and so far my post on a french forum did not have any reply (https://www.amigafrance.com/forums/topic/tester-un-pla-de-c64-avec-un-tl866-et-le-logiciel-minipro/), so I hope a minipro user coming here may be able to confirm that it is working ?

Here is the data to add to logicic.xml :

      <ic name="C64PLA" type="5" voltage="5V" pins="28">
        <vector id="00"> X X X X X X X X X Z Z Z Z G Z Z Z Z 1 X X X X X X X X V </vector>
        <vector id="01"> X X X X X X X X X L X X X G X X X H 0 1 1 0 1 X 1 X X V </vector>
        <vector id="02"> X 1 1 1 X X X X X L X X X G X X X H 0 X X 0 1 X 0 X X V </vector>
        <vector id="03"> X 1 0 1 X X 1 X X L X X X G X X X H 0 X X 0 0 1 0 X X V </vector>
        <vector id="04"> X 0 0 1 X X X X X X L X X G X X X H 0 X X 0 1 X 0 X X V </vector>
        <vector id="05"> X 0 0 1 X X 1 1 X X L X X G X X X H 0 X X X 0 1 0 X X V </vector>
        <vector id="06"> X 0 1 1 X 1 1 X X X X L X G X X X H 0 X X X X 0 0 X 1 V </vector>
        <vector id="07"> X 0 1 1 X X X X X X X L X G X X X H 0 X X 0 1 0 0 X 1 V </vector>
        <vector id="08"> X 0 1 1 X 1 0 1 X X X L X G X X X H 0 X X X X 0 0 X 1 V </vector>
        <vector id="09"> X 0 1 1 X 1 1 X X X X L X G X X X H 0 X X X X 1 0 1 1 V </vector>
        <vector id="10"> X 0 1 1 X X X X X X X L X G X X X H 0 X X 0 1 1 0 1 1 V </vector>
        <vector id="11"> X 0 1 1 X 1 0 1 X X X L X G X X X H 0 X X X X 1 0 1 1 V </vector>
        <vector id="12"> X 0 1 1 X X X X 0 X X X L G X X X X 0 X X X X 0 0 X 1 V </vector>
        <vector id="13"> X X X X 1 X X X X X X X X G L X X H 0 1 0 X 0 X 1 X X V </vector>
        <vector id="14"> X X X X 1 X X X X X X X X G L X X H 0 1 0 1 1 X 1 X X V </vector>
        <vector id="15"> X 0 1 1 X 0 1 X X X X X X G L X X H 0 X X 1 X 1 0 X 1 V </vector>
        <vector id="16"> X 0 1 1 X 0 0 1 X X X X X G L X X H 0 X X 1 X 1 0 X 1 V </vector>
        <vector id="17"> X 0 1 1 X 0 1 X X X X X X G L X X H 0 X X 0 0 1 0 X 1 V </vector>
        <vector id="18"> X 1 1 1 X X 1 X X X X X X G X L X H 0 X X 1 X 1 0 X X V </vector>
        <vector id="19"> X 1 1 1 X X 1 X X X X X X G X L X H 0 X X 0 0 1 0 X X V </vector>
        <vector id="20"> X 1 0 1 X X 1 1 X X X X X G X X X H 0 X X 1 X 1 0 X X V </vector>
        <vector id="21"> X X X X X X X X 1 X X X X G X X X H 0 X X X X X X X X V </vector>
        <vector id="22"> X X 1 0 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X X V </vector>
        <vector id="23"> X 1 0 X X X X X 0 X X X X G X X X H 0 X X 0 1 X X X X V </vector>
        <vector id="24"> X 0 0 0 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X 1 V </vector>
        <vector id="25"> X 0 1 1 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X 0 V </vector>
        <vector id="26"> X X X X X X X X X H H H H G H H H X 0 X X X X X X X X V </vector>
      </ic>

I am also interested to dump/test the C64 ROMs and maybe it would be possible without any hardware adapter ? In infoic.xml I see that there is a pin map but that does not allow to define which signal goes to which pin. And I haven't found such a definition in the code apart from sending a protocol ID to the programmer. For this I would like a bit more information about what it may be possible to do so I upvote for issue #237.

DavidGriffith commented 1 year ago

In GitLab by @landsfiskalen on Mar 13, 2023, 06:02

I'll check if it's working, I have a few C64:s here with working PLA:s to test with.

DavidGriffith commented 1 year ago

In GitLab by @landsfiskalen on Mar 14, 2023, 07:51

After adding the C64PLA to the logicic.xml, I get this when I run minipro -d C64PLA:

Found TL866II+ 04.2.132 (0x284)
Warning: Firmware is newer than expected.
  Expected  04.2.131 (0x283)
  Found     04.2.132 (0x284)
Name: C64PLA
Memory: 0 Bytes
Package: ICSP only
ICSP: -
Protocol: 0x00
Read buffer size: 0 Bytes
Write buffer size: 0 Bytes

Any idea what I'm doing wrong @f1ac0?

DavidGriffith commented 1 year ago

In GitLab by @f1ac0 on Mar 14, 2023, 12:16

If I am correct you need to add the "-T" command line argument to test a device with minipro.

About the name "C64PLA" that I put in the xml, it might be a good idea to use the chip marking instead (or in addition) which is "906114-01". Latest C64-C with "short boards" use a different chip known as "Super PLA" with "252535-01" marking that has different pinout and is not covered by this test.

DavidGriffith commented 1 year ago

In GitLab by @landsfiskalen on Mar 14, 2023, 16:34

Sorry, my bad @f1ac0, I used -d instead of -p together with -T. Now it works. :smile: I'll change it to the correct name "906114-01". Great way to check for defective PLA:s! Will check my stash to see if I have any bad PLA:s to test as well.

Found TL866II+ 04.2.132 (0x284)
Warning: Firmware is newer than expected.
  Expected  04.2.131 (0x283)
  Found     04.2.132 (0x284)
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Logic test successful.
DavidGriffith commented 1 year ago

In GitLab by @mthierer on May 6, 2023, 09:11

Thanks! I can confirm that this correctly identified both a known-good and a known-bad 906114-01.