Open DavidGriffith opened 1 year ago
In GitLab by @landsfiskalen on Mar 13, 2023, 06:02
I'll check if it's working, I have a few C64:s here with working PLA:s to test with.
In GitLab by @landsfiskalen on Mar 14, 2023, 07:51
After adding the C64PLA to the logicic.xml, I get this when I run minipro -d C64PLA:
Found TL866II+ 04.2.132 (0x284)
Warning: Firmware is newer than expected.
Expected 04.2.131 (0x283)
Found 04.2.132 (0x284)
Name: C64PLA
Memory: 0 Bytes
Package: ICSP only
ICSP: -
Protocol: 0x00
Read buffer size: 0 Bytes
Write buffer size: 0 Bytes
Any idea what I'm doing wrong @f1ac0?
In GitLab by @f1ac0 on Mar 14, 2023, 12:16
If I am correct you need to add the "-T" command line argument to test a device with minipro.
About the name "C64PLA" that I put in the xml, it might be a good idea to use the chip marking instead (or in addition) which is "906114-01". Latest C64-C with "short boards" use a different chip known as "Super PLA" with "252535-01" marking that has different pinout and is not covered by this test.
In GitLab by @landsfiskalen on Mar 14, 2023, 16:34
Sorry, my bad @f1ac0, I used -d instead of -p together with -T. Now it works. :smile: I'll change it to the correct name "906114-01". Great way to check for defective PLA:s! Will check my stash to see if I have any bad PLA:s to test as well.
Found TL866II+ 04.2.132 (0x284)
Warning: Firmware is newer than expected.
Expected 04.2.131 (0x283)
Found 04.2.132 (0x284)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
0000: X X X X X X X X X Z Z Z Z G Z Z Z Z 1 X X X X X X X X V
0001: X X X X X X X X X L X X X G X X X H 0 1 1 0 1 X 1 X X V
0002: X 1 1 1 X X X X X L X X X G X X X H 0 X X 0 1 X 0 X X V
0003: X 1 0 1 X X 1 X X L X X X G X X X H 0 X X 0 0 1 0 X X V
0004: X 0 0 1 X X X X X X L X X G X X X H 0 X X 0 1 X 0 X X V
0005: X 0 0 1 X X 1 1 X X L X X G X X X H 0 X X X 0 1 0 X X V
0006: X 0 1 1 X 1 1 X X X X L X G X X X H 0 X X X X 0 0 X 1 V
0007: X 0 1 1 X X X X X X X L X G X X X H 0 X X 0 1 0 0 X 1 V
0008: X 0 1 1 X 1 0 1 X X X L X G X X X H 0 X X X X 0 0 X 1 V
0009: X 0 1 1 X 1 1 X X X X L X G X X X H 0 X X X X 1 0 1 1 V
0010: X 0 1 1 X X X X X X X L X G X X X H 0 X X 0 1 1 0 1 1 V
0011: X 0 1 1 X 1 0 1 X X X L X G X X X H 0 X X X X 1 0 1 1 V
0012: X 0 1 1 X X X X 0 X X X L G X X X X 0 X X X X 0 0 X 1 V
0013: X X X X 1 X X X X X X X X G L X X H 0 1 0 X 0 X 1 X X V
0014: X X X X 1 X X X X X X X X G L X X H 0 1 0 1 1 X 1 X X V
0015: X 0 1 1 X 0 1 X X X X X X G L X X H 0 X X 1 X 1 0 X 1 V
0016: X 0 1 1 X 0 0 1 X X X X X G L X X H 0 X X 1 X 1 0 X 1 V
0017: X 0 1 1 X 0 1 X X X X X X G L X X H 0 X X 0 0 1 0 X 1 V
0018: X 1 1 1 X X 1 X X X X X X G X L X H 0 X X 1 X 1 0 X X V
0019: X 1 1 1 X X 1 X X X X X X G X L X H 0 X X 0 0 1 0 X X V
0020: X 1 0 1 X X 1 1 X X X X X G X X X H 0 X X 1 X 1 0 X X V
0021: X X X X X X X X 1 X X X X G X X X H 0 X X X X X X X X V
0022: X X 1 0 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X X V
0023: X 1 0 X X X X X 0 X X X X G X X X H 0 X X 0 1 X X X X V
0024: X 0 0 0 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X 1 V
0025: X 0 1 1 X X X X 0 X X X X G X X X H 0 X X 0 1 X X X 0 V
0026: X X X X X X X X X H H H H G H H H X 0 X X X X X X X X V
Logic test successful.
In GitLab by @mthierer on May 6, 2023, 09:11
Thanks! I can confirm that this correctly identified both a known-good and a known-bad 906114-01.
In GitLab by @f1ac0 on Mar 2, 2023, 14:38
Hi, This is not an issue.
The web page below shares how to test a Commodore 64 PLA using a TL866-II+ and Xgpro. http://www.breakintoprogram.co.uk/hardware/fixing-a-poorly-commodore-64-part-3
I believe it should also work a TL866 using minipro. I do not have a working chip to confirm and so far my post on a french forum did not have any reply (https://www.amigafrance.com/forums/topic/tester-un-pla-de-c64-avec-un-tl866-et-le-logiciel-minipro/), so I hope a minipro user coming here may be able to confirm that it is working ?
Here is the data to add to logicic.xml :
I am also interested to dump/test the C64 ROMs and maybe it would be possible without any hardware adapter ? In infoic.xml I see that there is a pin map but that does not allow to define which signal goes to which pin. And I haven't found such a definition in the code apart from sending a protocol ID to the programmer. For this I would like a bit more information about what it may be possible to do so I upvote for issue #237.