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DavidWigley / Digital-Logic-Final-Project

Final Project for ELEC 2275. Tic-Tac-Toe Verilog implementation.
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TODO #2

Open DavidWigley opened 7 years ago

DavidWigley commented 7 years ago

Logisim -need a way to signify someone has won, or delay the reset. -better UI (less clutter) -flag if input is > great (light an LED that just says invalid input) -rename the tunnels a bit better (who, trigu [wtf]) -tie in trigger for CPU (done)

Verilog fix

DavidWigley commented 7 years ago

Tina did UI and I think renamed tunnels.