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DavidWigley / Digital-Logic-Final-Project

Final Project for ELEC 2275. Tic-Tac-Toe Verilog implementation.
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Revamp isEmpty #4

Closed DavidWigley closed 7 years ago

DavidWigley commented 7 years ago

Turn all the is empty variables into one big array.

DavidWigley commented 7 years ago

Done. https://github.com/DavidWigley/Digital-Logic-Final-Project/commit/41134588f3b4c0a572d6d8e5843aaf92289b8f97