ADLS Group 13

[pgimenes]

• imported the activations, rtl and tb, and changed deps.py

• stream monitor + roller edge case + fifio wire bug + unpacked_reg bug

• emit verilog integration

• refactor - Verify Required Activations + Softmax

• gen sv updates, emit verilog dependence update

• docs except softmax

• silu doc had a small mistake

• alpha parameter for elu

• brought hardshrink from other branch

• file cleanup and bringing hardshrink from other branch

• emit verilog generates lut

• made 1 comment be on two lines

• more comments

• changed comments

• adding lut modules

• lut in tb

• code cleanup #1

• tested with luts (bardia)

• emit verilog tested and working

• added pipelining

• added bitstrign to pip reqs

• softmax tb

• softmax doc

• changed python files reformated using python3 -m black FILE_NAME

• formatted verilog files by hand

• removed a script

• verilog linter

• debug , adding linting to lut

• adding luts in efforts to pass ci bakhtiar

• bakhtiar: removing dir to fix ci

---