DeepWok / mase

Machine-Learning Accelerator System Exploration Tools
Other
108 stars 52 forks source link

lab4: Task 3, timescale not being automatically generated? #42

Closed bakhtiarZ closed 5 months ago

bakhtiarZ commented 5 months ago

commit: 9d7fc37ea506ad0c3519a771015148d36cf89142

command:

from chop.actions import simulate

simulate(skip_build=False, skip_test=False)

error: INFO: Running command perl /usr/bin/verilator -cc --exe -Mdir /home/bakhtiar/Documents/school/advanced_deep_learning_sys/lab4/sim_build -DCOCOTB_SIM=1 --top-module top --vpi --public-flat-rw --prefix Vtop -o top -LDFLAGS '-Wl,-rpath,/home/bakhtiar/.local/lib/python3.10/site-packages/cocotb/libs -L/home/bakhtiar/.local/lib/python3.10/site-packages/cocotb/libs -lcocotbvpi_verilator' -Wno-fatal -Wno-lint -Wno-style --trace -I/home/bakhtiar/.mase/top/hardware/rtl -I/home/bakhtiar/anaconda3/envs/mase/lib/python3.10/site-packages/mase_components/pycache/rtl /home/bakhtiar/.local/lib/python3.10/site-packages/cocotb/share/lib/verilator/verilator.cpp /home/bakhtiar/.mase/top/hardware/rtl/top.sv in directory /home/bakhtiar/Documents/school/advanced_deep_learning_sys/lab4/sim_build %Error-TIMESCALEMOD: /home/bakhtiar/.mase/top/hardware/rtl/top.sv:109:3: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2) /home/bakhtiar/.mase/top/hardware/rtl/top.sv:8:8: ... Location of module with timescale 8 | module top #( | ^~~ %Error-TIMESCALEMOD: /home/bakhtiar/.mase/top/hardware/rtl/top.sv:165:3: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2) /home/bakhtiar/.mase/top/hardware/rtl/top.sv:8:8: ... Location of module with timescale 8 | module top #( | ^~~ %Error: Exiting due to 2 error(s) ... See the manual and https://verilator.org/ for more assistance.

pgimenes commented 5 months ago

Try adding a line such as the following at the top of the generated RTL `timescale 1ns / 1ps

pgimenes commented 5 months ago

If this fixes the issue, you can submit a PR where this line is included in chop/passes/graph/transforms/verilog/emit_top.py

bakhtiarZ commented 5 months ago

I have put this on all files but I am still getting an error:

The output shows lines 109:3 has a missing timescale, on lines 109:3 of the top.sv is : fc1_inst, this is from this module instantiation:

`fixed_linear #( .DATA_IN_0_PRECISION_0(fc1_DATA_IN_0_PRECISION_0), // = 8 .DATA_IN_0_PRECISION_1(fc1_DATA_IN_0_PRECISION_1), // = 3 .DATA_IN_0_TENSOR_SIZE_DIM_0(fc1_DATA_IN_0_TENSOR_SIZE_DIM_0), // = 4 .DATA_IN_0_PARALLELISM_DIM_0(fc1_DATA_IN_0_PARALLELISM_DIM_0), // = 4 .DATA_IN_0_TENSOR_SIZE_DIM_1(fc1_DATA_IN_0_TENSOR_SIZE_DIM_1), // = 1 .DATA_IN_0_PARALLELISM_DIM_1(fc1_DATA_IN_0_PARALLELISM_DIM_1), // = 1 .WEIGHT_PRECISION_0(fc1_WEIGHT_PRECISION_0), // = 8 .WEIGHT_PRECISION_1(fc1_WEIGHT_PRECISION_1), // = 3 .WEIGHT_TENSOR_SIZE_DIM_0(fc1_WEIGHT_TENSOR_SIZE_DIM_0), // = 4 .WEIGHT_PARALLELISM_DIM_0(fc1_WEIGHT_PARALLELISM_DIM_0), // = 4 .WEIGHT_TENSOR_SIZE_DIM_1(fc1_WEIGHT_TENSOR_SIZE_DIM_1), // = 10 .WEIGHT_PARALLELISM_DIM_1(fc1_WEIGHT_PARALLELISM_DIM_1), // = 1 .BIAS_PRECISION_0(fc1_BIAS_PRECISION_0), // = 8 .BIAS_PRECISION_1(fc1_BIAS_PRECISION_1), // = 3 .BIAS_TENSOR_SIZE_DIM_0(fc1_BIAS_TENSOR_SIZE_DIM_0), // = 10 .BIAS_PARALLELISM_DIM_0(fc1_BIAS_PARALLELISM_DIM_0), // = 1 .DATA_OUT_0_PRECISION_0(fc1_DATA_OUT_0_PRECISION_0), // = 8 .DATA_OUT_0_PRECISION_1(fc1_DATA_OUT_0_PRECISION_1), // = 3 .DATA_OUT_0_TENSOR_SIZE_DIM_0(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_0), // = 10 .DATA_OUT_0_PARALLELISM_DIM_0(fc1_DATA_OUT_0_PARALLELISM_DIM_0), // = 4 .DATA_OUT_0_TENSOR_SIZE_DIM_1(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_1), // = 1 .DATA_OUT_0_PARALLELISM_DIM_1(fc1_DATA_OUT_0_PARALLELISM_DIM_1) ) fc1_inst ( .clk(clk), .rst(rst),

.data_in_0(fc1_data_in_0),
.data_in_0_valid(fc1_data_in_0_valid),
.data_in_0_ready(fc1_data_in_0_ready),

.data_out_0(fc1_data_out_0),
.data_out_0_valid(fc1_data_out_0_valid),
.data_out_0_ready(fc1_data_out_0_ready)

);`

It also shows 165:3 has a timescale missing, line 165 is "relu_inst" from the below snippet. `fixed_relu #( .DATA_IN_0_PRECISION_0(relu_DATA_IN_0_PRECISION_0), // = 8 .DATA_IN_0_PRECISION_1(relu_DATA_IN_0_PRECISION_1), // = 3 .DATA_IN_0_TENSOR_SIZE_DIM_0(relu_DATA_IN_0_TENSOR_SIZE_DIM_0), // = 10 .DATA_IN_0_PARALLELISM_DIM_0(relu_DATA_IN_0_PARALLELISM_DIM_0), // = 4 .DATA_IN_0_TENSOR_SIZE_DIM_1(relu_DATA_IN_0_TENSOR_SIZE_DIM_1), // = 1 .DATA_IN_0_PARALLELISM_DIM_1(relu_DATA_IN_0_PARALLELISM_DIM_1), // = 1 .INPLACE(relu_INPLACE), // = 0 .DATA_OUT_0_PRECISION_0(relu_DATA_OUT_0_PRECISION_0), // = 8 .DATA_OUT_0_PRECISION_1(relu_DATA_OUT_0_PRECISION_1), // = 3 .DATA_OUT_0_TENSOR_SIZE_DIM_0(relu_DATA_OUT_0_TENSOR_SIZE_DIM_0), // = 10 .DATA_OUT_0_PARALLELISM_DIM_0(relu_DATA_OUT_0_PARALLELISM_DIM_0), // = 4 .DATA_OUT_0_TENSOR_SIZE_DIM_1(relu_DATA_OUT_0_TENSOR_SIZE_DIM_1), // = 1 .DATA_OUT_0_PARALLELISM_DIM_1(relu_DATA_OUT_0_PARALLELISM_DIM_1) ) relu_inst ( .clk(clk), .rst(rst),

.data_in_0(relu_data_in_0),
.data_in_0_valid(relu_data_in_0_valid),
.data_in_0_ready(relu_data_in_0_ready),

.data_out_0(relu_data_out_0),
.data_out_0_valid(relu_data_out_0_valid),
.data_out_0_ready(relu_data_out_0_ready)

);` I added the timescale to both files but am still getting the error.

pgimenes commented 5 months ago

This relates to PR https://github.com/DeepWok/mase/pull/39 Solved offline