Feature Request: Verilog Lexer enhancement

[GoogleCodeExporter]

I know editra uses Scintilla and its lexers for syntax highlighting.  I 
find that a bit limiting for some languages.  I use VHDL, Verilog and 
SystemVerilog often.  The Verilog lexer is a bit out of date (I can help 
make a new lexer).

The enhancement I am looking for is to have multiple keyword/type,... 
categories with different colors.  For example SystemVerilog has Verilog 
keywords, and a number of new keywords.  There are a number of revisions 
for Verilog and SystemVerilog as well.  And on top of SystemVerilog, there 
are a number of classes and packages (VMM, OVM, URM, UVM, ...).  These 
define new types, interface, ...  It would be great if one could have 
multiple classes of keywords, types, ....

The other enhancement would be code completion for keywords, built-in 
methods, classes and class methods.

I am not sure how one would go about helping with any of these...
-- Amal

Original issue reported on code.google.com by akhailt...@gmail.com on 18 Mar 2010 at 5:38

[GoogleCodeExporter]

Hi,

Currently the stable release of wxPython has an older version of Scintilla (IIRC
v1.73) once wxPython 2.9/3.0 is out there will be a newer version to work with 
that I
think includes some improvements to the Verilog lexer.

Currently the Verilog/System Verilog languages support has 3 sets of keywords
available. They are currently split from Keywords/Types/Tasks. If you feel they 
are
not organized correctly please see Editra/src/syntax/_verilog.py and feel free 
to
suggest changes (patch).

The completion of Keywords is already supported, you can hit Ctrl+Space to 
bring up
completions for the current context of the caret.

You can write a custom lexer if the builtin scintilla one is not adequate, see
Editra\src\syntax\_xtext.py for an example of implementing a custom lexer in 
Editra.

Cody

Original comment by CodyPrec...@gmail.com on 18 Mar 2010 at 5:58

• Changed state: Investigate

[GoogleCodeExporter]

I have attached a modified version of _verilog.py that includes corrections to 
the 
keywords.  I also categorized them based on the standard versions.  The new 
SystemVerilog 2009 keywords are also included.

I have defined a couple of new categories (*_PREPROCESSORS and *_METHODS) but 
do not 
know what to do with them yet!  The *_PREPROCESSORS would be useful, but the 
lexer 
treats everything that starts with ` as a preprocessor keyword and does not 
care 
about the standard ones.

The *_METHODS would be good to have for SystemVerilog, but maybe those need to 
be 
used with the code completer.

I did not go for code elegance, but for clarity and the different standard 
categories 
of keywords.  Feel free to change the code as you fit.

I would be willing to spend more time enhancing this once I get better 
understanding 
of the source code and how things are done.  Especially the lexer and code 
completion  
need more attention.

Cheers,
-- Amal

Original comment by akhailt...@gmail.com on 23 Mar 2010 at 6:55

Attachments:

• _verilog.py

[GoogleCodeExporter]

Hi,

Could you please supply your changes as a patch based on the current svn?

Thanks,

Cody

Original comment by CodyPrec...@gmail.com on 24 Mar 2010 at 12:26

[GoogleCodeExporter]

Here is the patch based on the current updated SVN.

I will have a patch for the codebrowser plugin as well soon.

Cheers,
-- Amal

Original comment by akhailt...@gmail.com on 24 Mar 2010 at 2:08

Attachments:

• verilog_syntax.patch

[GoogleCodeExporter]

Hi,

I was reviewing your patch in preparation to apply it but the changes seem to 
be in
there twice?

could you please verify and correct this?

Thanks,

Cody

Original comment by CodyPrec...@gmail.com on 30 Mar 2010 at 3:05

• Changed state: Accepted

[GoogleCodeExporter]

Hi Cody,

I am not sure what part of the patch is repeated?!  I do not see any duplicates!

I organized the keywords based on language standard (Verilog 1995, 2001, SV 
2005 and SV 
2009).  Is that what you are referring to as twice?

-- Amal

Original comment by akhailt...@gmail.com on 30 Mar 2010 at 1:36

[GoogleCodeExporter]

Ah, sorry my eyes where playing tricks on me last night. The Verilog and System
Verilog sections looked to be the same when I looked at it, but I see that they 
are
different.

Original comment by CodyPrec...@gmail.com on 30 Mar 2010 at 1:46

[GoogleCodeExporter]

Applied with minor formatting changes.

Thanks!

Original comment by CodyPrec...@gmail.com on 31 Mar 2010 at 12:03

• Changed state: Fixed
• Added labels: Type-Patch
• Removed labels: Type-Defect