DerrickYLJ / Blocking_Waived_Estimation

This repo aims to solve worst case delay of relatively complicated network architecture with [1] Trajectory Approach; [2] Network Calculus; [3] Compositional Performance Analysis (CPA); and [4] Flow Aggregation and summarize both advantages and disadvantages of each approach and strives to seek out the optimal method under specific scenarios.
2 stars 0 forks source link

Meeting Oct 24th & Nov 8th & Nov 22nd, CPA_S and CPA_W correction + Simulation code&results #5

Open DerrickYLJ opened 10 months ago

DerrickYLJ commented 10 months ago

Any curve below the Ernst curve is not possible to achieve since Ernst curve represents the lowest theoretical possible delay

Screen Shot 2023-10-24 at 11 24 24 PM

Any curve below the Ernst curve is not possible to be achieved since Ernst curve represents the lowest theoretical possible delay.

DerrickYLJ commented 10 months ago

In our architecture, RTA, CPA_S, and FA are logically the same and will output very similar answers under the assumptions in FA.

DerrickYLJ commented 10 months ago

The discussing points:

DerrickYLJ commented 10 months ago

4 From Professor Song's Comments:

@DerrickYLJ Contrary to what I've said during our last meeting, unfortunately I did not find time to reproduce more simulation traces, neither to verify the existing traces. I put here the simulation model that I've built using "java modelling tools" https://jmt.sourceforge.net/ I put also the first simulation traces produced two or three weeks ago. If you have time before next Wednesday, maybe you can take a look on the different traces to verify if the e2e delays are correct or wrong, especially for those VLs having higher simulation delays than the theoretics given by RTA and CPA-S and FA (I see at least VL1, VL2, VL7 and VL8). You can see for example if the e2e delays are consistent with the local delays on their paths. Otherwise, no worry, we can discuss Wednesday to make clear the next step. Here is the screenshot of the model: Capture d’écran 2023-10-23 à 09 11 40

And simulation traces:

SWaToES3_VL13_Response Time.csv SWaToES3_VL9_Response Time.csv SWaToES3_VL7_Response Time.csv SWaToES3_VL3_Response Time.csv SWaToES3_VL11_Response Time.csv SWaToES3_VL8_Response Time.csv SWaToES3_VL4_Response Time.csv SWbToES2_VL12_Response Time.csv VL13_System Response Time.csv VL6_System Response Time.csv VL10_System Response Time.csv VL5_System Response Time.csv VL9_System Response Time.csv VL7_System Response Time.csv VL3_System Response Time.csv VL2_System Response Time.csv VL11_System Response Time.csv VL8_System Response Time.csv VL4_System Response Time.csv SWaToES1_VL6_Response Time.csv SWaToES1_VL12_Response Time.csv SWaToES1_VL5_Response Time.csv SWaToES1_VL9_Response Time.csv SWaToES1_VL7_Response Time.csv SWaToES1_VL2_Response Time.csv SWbToES4_VL10_Response Time.csv SWbToES4_VL9_Response Time.csv SWbToES4_VL11_Response Time.csv SWbToES2_VL11_Response Time.csv SWbToES2_VL8_Response Time.csv SWbToSWa_VL13_Response Time.csv SWbToSWa_VL6_Response Time.csv SWbToSWa_VL9_Response Time.csv SWbToSWa_VL7_Response Time.csv SWbToSWa_VL3_Response Time.csv SWbToSWa_VL2_Response Time.csv SWaToSWb_VL12_Response Time.csv SWaToSWb_VL10_Response Time.csv SWaToSWb_VL11_Response Time.csv SWaToSWb_VL8_Response Time.csv ES4toSWb_VL13_Response Time.csv ES4toSWb_VL6_Response Time.csv ES3toSWa_VL12_Response Time.csv ES3toSWa_VL10_Response Time.csv ES2toSWb_VL9_Response Time.csv ES2toSWb_VL7_Response Time.csv ES2toSWb_VL3_Response Time.csv ES2toSWb_VL2_Response Time.csv ES1toSWa_VL11_Response Time.csv ES1toSWa_VL8_Response Time.csv ES1toSWa_VL4_Response Time.csv SWbToES2_VL1_Response Time.csv SWaToSWb_VL1_Response Time.csv VL1_System Response Time.csv ES1toSWa_VL1_Response Time.csv ES3toSWa_VL5_Response Time.csv VL12_System Response Time.csv

DerrickYLJ commented 10 months ago

resolved.

DerrickYLJ commented 10 months ago

Update the new result for RTA without the assumption that any VLs block the target VL won't block it once again. The updated results are below:

Screen Shot 2023-11-08 at 1 17 13 AM

data_rta = [417.0, 471.0, 507.0, 340.0, 183.0, 350.0, 744.0, 533.0, 744.0, 511.0, 632.0, 396.0, 609.0] data_cpa_w = [417, 471, 507, 340, 183, 350, 744, 533, 744, 511, 632, 396, 609] first_simulation_ernst = [371, 401, 401, 293, 58, 128, 467, 415, 453, 112, 415, 126, 150] NC_PK = [401.911, 420.994, 443.627, 312.160, 266.764, 420.212, 699.366, 507.494, 699.366, 465.147, 620.064, 255.920, 563.543]

Observation: RTA and CPA_W are outputting the same results.

Task:

DerrickYLJ commented 9 months ago

CPA_S Correction:

case 1 : VL1

ES1 -> (VL4 + VL11) -> Switch A -> (VL11) -> Switch B -> (VL11) -> ES2 path P1 e2e latency. best case: 6, worst case: 417 From PyCPA.

If blocking factor is greater than target wcd, we apply the rule; otherwise, only blocking it once.