search

Dhruv-Acharya / Gem5ToMcPAT-Parser

Gem5 to McPAT parser with multicore and cache support
MIT License
7 stars 12 forks source link

Getting Error for Unexpected EOF #1

Open sauravmalla4 opened 5 years ago

sauravmalla4 commented 5 years ago

Hello Dhruv, I am getting an error for the Conversion of the gem5 O/P to mcPAT input as Follows

Traceback (most recent call last): File "Gem5ToMcPAT-Parser.py", line 299, in main() File "Gem5ToMcPAT-Parser.py", line 296, in main dumpMcpatOut(args.output) File "Gem5ToMcPAT-Parser.py", line 262, in dumpMcpatOut exprs[i] = str(eval(exprs[i])) File "", line 1 {u'do_statistics_insts': True ^ SyntaxError: unexpected EOF while parsing

I am Parsing the Output of blackscholes_4c_simsmall.rcS for Parsec Benchmark in gem5. Here is my Config.json file

{ "name": null, "sim_quantum": 0, "system": { "kernel": "/home/saurav/IITG/full_sys_simu/system/binaries/vmlinux", "mmap_using_noreserve": false, "kernel_addr_check": true, "bridge": { "ranges": [ "8796093022208:18446744073709551615:0:0:0:0" ], "slave": { "peer": "system.membus.master[0]", "role": "SLAVE" }, "name": "bridge", "p_state_clk_gate_min": 1000, "p_state_clk_gate_bins": 20, "cxx_class": "Bridge", "req_size": 16, "clk_domain": "system.clk_domain", "power_model": null, "delay": 50000, "eventq_index": 0, "master": { "peer": "system.iobus.slave[0]", "role": "MASTER" }, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.bridge", "resp_size": 16, "type": "Bridge" }, "iobus": { "forward_latency": 1, "slave": { "peer": [ "system.bridge.master", "system.tsunami.ide.dma", "system.tsunami.ethernet.dma" ], "role": "SLAVE" }, "name": "iobus", "p_state_clk_gate_min": 1000, "p_state_clk_gate_bins": 20, "cxx_class": "NoncoherentXBar", "clk_domain": "system.clk_domain", "power_model": null, "width": 16, "eventq_index": 0, "master": { "peer": [ "system.tsunami.cchip.pio", "system.tsunami.pchip.pio", "system.tsunami.fake_sm_chip.pio", "system.tsunami.fake_uart1.pio", "system.tsunami.fake_uart2.pio", "system.tsunami.fake_uart3.pio", "system.tsunami.fake_uart4.pio", "system.tsunami.fake_ppc.pio", "system.tsunami.fake_OROM.pio", "system.tsunami.fake_pnp_addr.pio", "system.tsunami.fake_pnp_write.pio", "system.tsunami.fake_pnp_read0.pio", "system.tsunami.fake_pnp_read1.pio", "system.tsunami.fake_pnp_read2.pio", "system.tsunami.fake_pnp_read3.pio", "system.tsunami.fake_pnp_read4.pio", "system.tsunami.fake_pnp_read5.pio", "system.tsunami.fake_pnp_read6.pio", "system.tsunami.fake_pnp_read7.pio", "system.tsunami.fake_ata0.pio", "system.tsunami.fake_ata1.pio", "system.tsunami.fb.pio", "system.tsunami.io.pio", "system.tsunami.uart.pio", "system.tsunami.backdoor.pio", "system.tsunami.ide.pio", "system.tsunami.ethernet.pio", "system.iocache.cpu_side" ], "role": "MASTER" }, "response_latency": 2, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.iobus", "type": "NoncoherentXBar", "use_default_range": false, "frontend_latency": 2 }, "work_end_exit_count": 0, "symbolfile": "", "tsunami": { "fake_uart1": { "pio": { "peer": "system.iobus.master[3]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848696, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_uart1", "ret_data16": 65535, "ret_data8": 255, "name": "fake_uart1", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_uart2": { "pio": { "peer": "system.iobus.master[4]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848936, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_uart2", "ret_data16": 65535, "ret_data8": 255, "name": "fake_uart2", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_uart3": { "pio": { "peer": "system.iobus.master[5]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848680, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_uart3", "ret_data16": 65535, "ret_data8": 255, "name": "fake_uart3", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_uart4": { "pio": { "peer": "system.iobus.master[6]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848944, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_uart4", "ret_data16": 65535, "ret_data8": 255, "name": "fake_uart4", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_ppc": { "pio": { "peer": "system.iobus.master[7]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848891, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_ppc", "ret_data16": 65535, "ret_data8": 255, "name": "fake_ppc", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "cchip": { "name": "cchip", "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[0]", "role": "SLAVE" }, "p_state_clk_gate_bins": 20, "cxx_class": "TsunamiCChip", "pio_latency": 100000, "clk_domain": "system.clk_domain", "power_model": null, "system": "system", "tsunami": "system.tsunami", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.tsunami.cchip", "pio_addr": 8803072344064, "type": "TsunamiCChip" }, "io": { "pio": { "peer": "system.iobus.master[22]", "role": "SLAVE" }, "name": "io", "p_state_clk_gate_min": 1000, "year_is_bcd": false, "p_state_clk_gate_bins": 20, "cxx_class": "TsunamiIO", "pio_latency": 100000, "clk_domain": "system.clk_domain", "power_model": null, "system": "system", "tsunami": "system.tsunami", "frequency": 976562500, "eventq_index": 0, "time": "Thu Jan 1 00:00:00 2009", "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.tsunami.io", "pio_addr": 8804615847936, "type": "TsunamiIO" }, "cxx_class": "Tsunami", "pchip": { "pio": { "peer": "system.iobus.master[1]", "role": "SLAVE" }, "cxx_class": "TsunamiPChip", "system": "system", "conf_size": 16777216, "pio_addr": 8802535473152, "pci_mem_base": 8796093022208, "conf_device_bits": 8, "pio_latency": 100000, "clk_domain": "system.clk_domain", "platform": "system.tsunami", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "pci_pio_base": 8804615847936, "type": "TsunamiPChip", "p_state_clk_gate_min": 1000, "conf_base": 8804649402368, "power_model": null, "path": "system.tsunami.pchip", "name": "pchip", "p_state_clk_gate_bins": 20, "tsunami": "system.tsunami", "pci_dma_base": 0 }, "fake_ata1": { "pio": { "peer": "system.iobus.master[20]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848304, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_ata1", "ret_data16": 65535, "ret_data8": 255, "name": "fake_ata1", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_ata0": { "pio": { "peer": "system.iobus.master[19]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848432, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_ata0", "ret_data16": 65535, "ret_data8": 255, "name": "fake_ata0", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "system": "system", "backdoor": { "name": "backdoor", "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[24]", "role": "SLAVE" }, "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", "power_model": null, "system": "system", "terminal": "system.terminal", "platform": "system.tsunami", "eventq_index": 0, "cxx_class": "AlphaBackdoor", "p_state_clk_gate_max": 1000000000000, "path": "system.tsunami.backdoor", "pio_addr": 8804682956800, "disk": "system.simple_disk", "type": "AlphaBackdoor", "cpu": "system.cpu" }, "eventq_index": 0, "fake_pnp_read3": { "pio": { "peer": "system.iobus.master[14]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848643, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read3", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read3", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read2": { "pio": { "peer": "system.iobus.master[13]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848579, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read2", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read2", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read1": { "pio": { "peer": "system.iobus.master[12]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848515, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read1", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read1", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read0": { "pio": { "peer": "system.iobus.master[11]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848451, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read0", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read0", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read7": { "pio": { "peer": "system.iobus.master[18]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848899, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read7", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read7", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read6": { "pio": { "peer": "system.iobus.master[17]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848835, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read6", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read6", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read5": { "pio": { "peer": "system.iobus.master[16]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848771, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read5", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read5", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_read4": { "pio": { "peer": "system.iobus.master[15]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848707, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_read4", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_read4", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_pnp_write": { "pio": { "peer": "system.iobus.master[10]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615850617, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_write", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_write", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fb": { "devicename": "FrameBuffer", "name": "fb", "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[21]", "role": "SLAVE" }, "p_state_clk_gate_bins": 20, "cxx_class": "BadDevice", "pio_latency": 100000, "clk_domain": "system.clk_domain", "power_model": null, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.tsunami.fb", "pio_addr": 8804615848912, "type": "BadDevice" }, "path": "system.tsunami", "fake_pnp_addr": { "pio": { "peer": "system.iobus.master[9]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848569, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_pnp_addr", "ret_data16": 65535, "ret_data8": 255, "name": "fake_pnp_addr", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "fake_OROM": { "pio": { "peer": "system.iobus.master[8]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8796093677568, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_OROM", "ret_data16": 65535, "ret_data8": 255, "name": "fake_OROM", "ret_bad_addr": false, "pio_size": 393216, "p_state_clk_gate_bins": 20 }, "name": "tsunami", "uart": { "name": "uart", "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[23]", "role": "SLAVE" }, "p_state_clk_gate_bins": 20, "cxx_class": "Uart8250", "pio_latency": 100000, "clk_domain": "system.clk_domain", "power_model": null, "system": "system", "terminal": "system.terminal", "platform": "system.tsunami", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "path": "system.tsunami.uart", "pio_addr": 8804615848952, "type": "Uart8250" }, "type": "Tsunami", "fake_sm_chip": { "pio": { "peer": "system.iobus.master[2]", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 8804615848816, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.tsunami.fake_sm_chip", "ret_data16": 65535, "ret_data8": 255, "name": "fake_sm_chip", "ret_bad_addr": false, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "intrctrl": "system.intrctrl", "ethernet": { "PMCAPNextCapability": 0, "InterruptPin": 1, "HeaderType": 0, "VendorID": 4107, "MSIXMsgCtrl": 0, "MSIXCAPNextCapability": 0, "PXCAPLinkCtrl": 0, "Revision": 0, "hardware_address": "00:90:00:00:00:01", "LegacyIOBase": 0, "pio_latency": 30000, "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, "PXCAPDevCapabilities": 0, "MSIXCAPCapId": 0, "BAR3Size": 0, "power_model": null, "intr_delay": 10000000, "PXCAPCapabilities": 0, "tx_thread": false, "SubsystemID": 0, "PXCAPCapId": 0, "BAR4": 0, "BAR1": 0, "BAR0": 1, "BAR3": 0, "BAR2": 0, "BAR5": 0, "PXCAPDevStatus": 0, "BAR2Size": 0, "MSICAPNextCapability": 0, "ExpansionROM": 0, "dma_no_allocate": true, "MSICAPMsgCtrl": 0, "BAR5Size": 0, "tx_delay": 1000000, "CardbusCIS": 0, "MSIXPbaOffset": 0, "rx_thread": false, "MSICAPBaseOffset": 0, "MaximumLatency": 52, "BAR2LegacyIO": false, "rx_filter": true, "LatencyTimer": 0, "BAR4LegacyIO": false, "p_state_clk_gate_max": 1000000000000, "PXCAPLinkStatus": 0, "PXCAPDevCap2": 0, "p_state_clk_gate_min": 1000, "rx_delay": 1000000, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, "host": "system.tsunami.pchip", "Command": 0, "SubClassCode": 0, "pci_func": 0, "BAR5LegacyIO": false, "MSICAPMsgData": 0, "BIST": 0, "PXCAPDevCtrl2": 0, "pci_bus": 0, "InterruptLine": 30, "MSICAPMsgAddr": 0, "BAR3LegacyIO": false, "BAR4Size": 0, "path": "system.tsunami.ethernet", "MinimumGrant": 176, "Status": 656, "BAR0Size": 256, "system": "system", "name": "ethernet", "PXCAPNextCapability": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "type": "NSGigE", "tx_fifo_size": 524288, "PXCAPBaseOffset": 0, "DeviceID": 34, "CacheLineSize": 0, "rss": false, "dma": { "peer": "system.iobus.slave[2]", "role": "MASTER" }, "PMCAPCapId": 0, "dma_read_delay": 0, "dma_read_factor": 0, "config_latency": 20000, "BAR1Size": 4096, "dma_write_factor": 0, "pio": { "peer": "system.iobus.master[26]", "role": "SLAVE" }, "pci_dev": 1, "PMCAPCtrlStatus": 0, "cxx_class": "NSGigE", "dma_data_free": false, "dma_write_delay": 0, "clk_domain": "system.clk_domain", "SubsystemVendorID": 0, "PMCAPBaseOffset": 0, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, "MSICAPCapId": 0, "BAR0LegacyIO": false, "ProgIF": 0, "BAR1LegacyIO": false, "PMCAPCapabilities": 0, "dma_desc_free": false, "ClassCode": 2, "p_state_clk_gate_bins": 20, "rx_fifo_size": 524288 }, "ide": { "PMCAPNextCapability": 0, "InterruptPin": 1, "HeaderType": 0, "VendorID": 32902, "MSIXMsgCtrl": 0, "MSIXCAPNextCapability": 0, "PXCAPLinkCtrl": 0, "Revision": 0, "LegacyIOBase": 0, "pio_latency": 30000, "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, "PXCAPDevCapabilities": 0, "MSIXCAPCapId": 0, "BAR3Size": 4, "power_model": null, "PXCAPCapabilities": 0, "SubsystemID": 0, "PXCAPCapId": 0, "BAR4": 1, "BAR1": 1, "BAR0": 1, "BAR3": 1, "BAR2": 1, "BAR5": 1, "PXCAPDevStatus": 0, "disks": [ "system.disk0", "system.disk2" ], "BAR2Size": 8, "MSICAPNextCapability": 0, "ExpansionROM": 0, "MSICAPMsgCtrl": 0, "BAR5Size": 0, "CardbusCIS": 0, "MSIXPbaOffset": 0, "MSICAPBaseOffset": 0, "MaximumLatency": 0, "BAR2LegacyIO": false, "LatencyTimer": 0, "BAR4LegacyIO": false, "p_state_clk_gate_max": 1000000000000, "PXCAPLinkStatus": 0, "PXCAPDevCap2": 0, "p_state_clk_gate_min": 1000, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, "host": "system.tsunami.pchip", "Command": 0, "SubClassCode": 1, "pci_func": 0, "BAR5LegacyIO": false, "MSICAPMsgData": 0, "BIST": 0, "PXCAPDevCtrl2": 0, "pci_bus": 0, "InterruptLine": 31, "MSICAPMsgAddr": 0, "BAR3LegacyIO": false, "BAR4Size": 16, "path": "system.tsunami.ide", "MinimumGrant": 0, "Status": 640, "BAR0Size": 8, "system": "system", "name": "ide", "PXCAPNextCapability": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "type": "IdeController", "ctrl_offset": 0, "PXCAPBaseOffset": 0, "DeviceID": 28945, "io_shift": 0, "CacheLineSize": 0, "dma": { "peer": "system.iobus.slave[1]", "role": "MASTER" }, "PMCAPCapId": 0, "config_latency": 20000, "BAR1Size": 4, "pio": { "peer": "system.iobus.master[25]", "role": "SLAVE" }, "pci_dev": 0, "PMCAPCtrlStatus": 0, "cxx_class": "IdeController", "clk_domain": "system.clk_domain", "SubsystemVendorID": 0, "PMCAPBaseOffset": 0, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, "MSICAPCapId": 0, "BAR0LegacyIO": false, "ProgIF": 133, "BAR1LegacyIO": false, "PMCAPCapabilities": 0, "ClassCode": 1, "p_state_clk_gate_bins": 20 } }, "readfile": "./blackscholes_4c_simsmall.rcS", "thermal_model": null, "system_type": 34, "cxx_class": "LinuxAlphaSystem", "work_begin_cpu_id_exit": -1, "load_offset": 0, "terminal": { "name": "terminal", "output": true, "number": 0, "intr_control": "system.intrctrl", "eventq_index": 0, "cxx_class": "Terminal", "path": "system.terminal", "type": "Terminal", "port": 3456 }, "work_begin_exit_count": 0, "console": "/home/saurav/IITG/full_sys_simu/system/binaries/console", "p_state_clk_gate_min": 1000, "disk0": { "driveID": "master", "name": "disk0", "image": { "read_only": false, "name": "image", "cxx_class": "CowDiskImage", "eventq_index": 0, "child": { "read_only": true, "name": "child", "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.disk0.image.child", "image_file": "/home/saurav/IITG/full_sys_simu/system/disks/linux-parsec-2-1-m5-with-test-inputs.img", "type": "RawDiskImage" }, "path": "system.disk0.image", "image_file": "", "type": "CowDiskImage", "table_size": 65536 }, "delay": 1000000, "eventq_index": 0, "cxx_class": "IdeDisk", "path": "system.disk0", "type": "IdeDisk" }, "memories": [ "system.mem_ctrls" ], "disk2": { "driveID": "master", "name": "disk2", "image": { "read_only": false, "name": "image", "cxx_class": "CowDiskImage", "eventq_index": 0, "child": { "read_only": true, "name": "child", "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.disk2.image.child", "image_file": "/home/saurav/IITG/full_sys_simu/system/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.disk2.image", "image_file": "", "type": "CowDiskImage", "table_size": 65536 }, "delay": 1000000, "eventq_index": 0, "cxx_class": "IdeDisk", "path": "system.disk2", "type": "IdeDisk" }, "work_begin_ckpt_count": 0, "clk_domain": { "name": "clk_domain", "clock": [ 1000 ], "init_perf_level": 0, "voltage_domain": "system.voltage_domain", "eventq_index": 0, "cxx_class": "SrcClockDomain", "path": "system.clk_domain", "type": "SrcClockDomain", "domain_id": -1 }, "mem_ranges": [ "0:536870911:0:0:0:0" ], "membus": { "point_of_coherency": true, "system": "system", "response_latency": 2, "cxx_class": "CoherentXBar", "badaddr_responder": { "pio": { "peer": "system.membus.default", "role": "SLAVE" }, "ret_data64": 18446744073709551615, "fake_mem": false, "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", "pio_addr": 0, "update_data": false, "warn_access": "", "pio_latency": 100000, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", "p_state_clk_gate_min": 1000, "power_model": null, "ret_data32": 4294967295, "path": "system.membus.badaddr_responder", "ret_data16": 65535, "ret_data8": 255, "name": "badaddr_responder", "ret_bad_addr": true, "pio_size": 8, "p_state_clk_gate_bins": 20 }, "forward_latency": 4, "clk_domain": "system.clk_domain", "width": 16, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "master": { "peer": [ "system.bridge.slave", "system.mem_ctrls.port" ], "role": "MASTER" }, "type": "CoherentXBar", "frontend_latency": 3, "slave": { "peer": [ "system.system_port", "system.iocache.mem_side", "system.l2.mem_side" ], "role": "SLAVE" }, "p_state_clk_gate_min": 1000, "snoop_filter": { "name": "snoop_filter", "system": "system", "max_capacity": 8388608, "eventq_index": 0, "cxx_class": "SnoopFilter", "path": "system.membus.snoop_filter", "type": "SnoopFilter", "lookup_latency": 1 }, "power_model": null, "path": "system.membus", "snoop_response_latency": 4, "name": "membus", "default": { "peer": "system.membus.badaddr_responder.pio", "role": "MASTER" }, "p_state_clk_gate_bins": 20, "use_default_range": false }, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "iocache": { "cpu_side": { "peer": "system.iobus.master[27]", "role": "SLAVE" }, "clusivity": "mostly_incl", "prefetcher": null, "system": "system", "write_buffers": 8, "response_latency": 50, "cxx_class": "Cache", "size": 1024, "type": "Cache", "clk_domain": "system.clk_domain", "max_miss_count": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.membus.slave[1]", "role": "MASTER" }, "mshrs": 20, "writeback_clean": false, "p_state_clk_gate_min": 1000, "tags": { "size": 1024, "tag_latency": 50, "name": "tags", "p_state_clk_gate_min": 1000, "eventq_index": 0, "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "power_model": null, "sequential_access": false, "assoc": 8, "cxx_class": "LRU", "p_state_clk_gate_max": 1000000000000, "path": "system.iocache.tags", "block_size": 64, "type": "LRU", "data_latency": 50 }, "tgts_per_mshr": 12, "demand_mshr_reserve": 1, "power_model": null, "addr_ranges": [ "0:536870911:0:0:0:0" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.iocache", "data_latency": 50, "tag_latency": 50, "name": "iocache", "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 8 }, "dvfs_handler": { "enable": false, "name": "dvfs_handler", "sys_clk_domain": "system.clk_domain", "transition_latency": 100000000, "eventq_index": 0, "cxx_class": "DVFSHandler", "domains": [], "path": "system.dvfs_handler", "type": "DVFSHandler" }, "system_rev": 1024, "type": "LinuxAlphaSystem", "boot_cpu_frequency": 500, "voltage_domain": { "name": "voltage_domain", "eventq_index": 0, "voltage": [ "1.0" ], "cxx_class": "VoltageDomain", "path": "system.voltage_domain", "type": "VoltageDomain" }, "cache_line_size": 64, "boot_osflags": "root=/dev/hda1 console=ttyS0", "system_port": { "peer": "system.membus.slave[0]", "role": "MASTER" }, "power_model": null, "simple_disk": { "name": "simple_disk", "system": "system", "eventq_index": 0, "cxx_class": "SimpleDisk", "path": "system.simple_disk", "disk": { "read_only": true, "name": "disk", "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.simple_disk.disk", "image_file": "/home/saurav/IITG/full_sys_simu/system/disks/linux-parsec-2-1-m5-with-test-inputs.img", "type": "RawDiskImage" }, "type": "SimpleDisk" }, "work_cpus_ckpt_count": 0, "thermal_components": [], "path": "system", "switch_cpus": [ { "do_statistics_insts": true, "numThreads": 1, "itb": { "name": "itb", "eventq_index": 0, "cxx_class": "AlphaISA::TLB", "path": "system.switch_cpus.itb", "type": "AlphaTLB", "size": 48 }, "simulate_data_stalls": false, "function_trace": false, "do_checkpoint_insts": true, "cxx_class": "AtomicSimpleCPU", "max_loads_all_threads": 0, "system": "system", "clk_domain": "system.cpu_clk_domain", "function_trace_start": 0, "cpu_id": 0, "width": 1, "checker": null, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "do_quiesce": true, "type": "AtomicSimpleCPU", "fastmem": false, "profile": 0, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, "interrupts": [], "socket_id": 0, "power_model": null, "max_insts_all_threads": 0, "path": "system.switch_cpus", "max_loads_any_thread": 0, "switched_out": true, "workload": [], "name": "switch_cpus", "dtb": { "name": "dtb", "eventq_index": 0, "cxx_class": "AlphaISA::TLB", "path": "system.switch_cpus.dtb", "type": "AlphaTLB", "size": 64 }, "simpoint_start_insts": [], "max_insts_any_thread": 0, "simulate_inst_stalls": false, "progress_interval": 0, "branchPred": null, "isa": [ { "name": "isa", "system": "system", "eventq_index": 0, "cxx_class": "AlphaISA::ISA", "path": "system.switch_cpus.isa", "type": "AlphaISA" } ], "tracer": { "eventq_index": 0, "path": "system.switch_cpus.tracer", "type": "ExeTracer", "name": "tracer", "cxx_class": "Trace::ExeTracer" } } ], "pal": "/home/saurav/IITG/full_sys_simu/system/binaries/ts_osfpal", "cpu_clk_domain": { "name": "cpu_clk_domain", "clock": [ 500 ], "init_perf_level": 0, "voltage_domain": "system.cpu_voltage_domain", "eventq_index": 0, "cxx_class": "SrcClockDomain", "path": "system.cpu_clk_domain", "type": "SrcClockDomain", "domain_id": -1 }, "tol2bus": { "point_of_coherency": false, "system": "system", "response_latency": 1, "cxx_class": "CoherentXBar", "forward_latency": 0, "clk_domain": "system.cpu_clk_domain", "width": 32, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "master": { "peer": [ "system.l2.cpu_side" ], "role": "MASTER" }, "type": "CoherentXBar", "frontend_latency": 1, "slave": { "peer": [ "system.cpu.icache.mem_side", "system.cpu.dcache.mem_side" ], "role": "SLAVE" }, "p_state_clk_gate_min": 1000, "snoop_filter": { "name": "snoop_filter", "system": "system", "max_capacity": 8388608, "eventq_index": 0, "cxx_class": "SnoopFilter", "path": "system.tol2bus.snoop_filter", "type": "SnoopFilter", "lookup_latency": 0 }, "power_model": null, "path": "system.tol2bus", "snoop_response_latency": 1, "name": "tol2bus", "p_state_clk_gate_bins": 20, "use_default_range": false }, "work_end_ckpt_count": 0, "mem_mode": "atomic", "name": "system", "init_param": 0, "p_state_clk_gate_bins": 20, "load_addr_mask": 1099511627775, "cpu": [ { "do_statistics_insts": true, "numThreads": 1, "itb": { "name": "itb", "eventq_index": 0, "cxx_class": "AlphaISA::TLB", "path": "system.cpu.itb", "type": "AlphaTLB", "size": 48 }, "simulate_data_stalls": false, "icache": { "cpu_side": { "peer": "system.cpu.icache_port", "role": "SLAVE" }, "clusivity": "mostly_incl", "prefetcher": null, "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "type": "Cache", "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.tol2bus.slave[0]", "role": "MASTER" }, "mshrs": 4, "writeback_clean": true, "p_state_clk_gate_min": 1000, "tags": { "size": 32768, "tag_latency": 2, "name": "tags", "p_state_clk_gate_min": 1000, "eventq_index": 0, "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", "power_model": null, "sequential_access": false, "assoc": 2, "cxx_class": "LRU", "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.icache.tags", "block_size": 64, "type": "LRU", "data_latency": 2 }, "tgts_per_mshr": 20, "demand_mshr_reserve": 1, "power_model": null, "addr_ranges": [ "0:18446744073709551615:0:0:0:0" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu.icache", "data_latency": 2, "tag_latency": 2, "name": "icache", "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 2 }, "function_trace": false, "do_checkpoint_insts": true, "cxx_class": "AtomicSimpleCPU", "max_loads_all_threads": 0, "system": "system", "clk_domain": "system.cpu_clk_domain", "function_trace_start": 0, "cpu_id": 0, "width": 1, "checker": null, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "do_quiesce": true, "type": "AtomicSimpleCPU", "fastmem": false, "profile": 0, "icache_port": { "peer": "system.cpu.icache.cpu_side", "role": "MASTER" }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, "path": "system.cpu.interrupts", "type": "AlphaInterrupts", "name": "interrupts", "cxx_class": "AlphaISA::Interrupts" } ], "dcache_port": { "peer": "system.cpu.dcache.cpu_side", "role": "MASTER" }, "socket_id": 0, "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu", "max_loads_any_thread": 0, "switched_out": false, "workload": [], "name": "cpu", "dtb": { "name": "dtb", "eventq_index": 0, "cxx_class": "AlphaISA::TLB", "path": "system.cpu.dtb", "type": "AlphaTLB", "size": 64 }, "simpoint_start_insts": [], "max_insts_any_thread": 50000000000, "simulate_inst_stalls": false, "progress_interval": 0, "branchPred": null, "dcache": { "cpu_side": { "peer": "system.cpu.dcache_port", "role": "SLAVE" }, "clusivity": "mostly_incl", "prefetcher": null, "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 65536, "type": "Cache", "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.tol2bus.slave[1]", "role": "MASTER" }, "mshrs": 4, "writeback_clean": false, "p_state_clk_gate_min": 1000, "tags": { "size": 65536, "tag_latency": 2, "name": "tags", "p_state_clk_gate_min": 1000, "eventq_index": 0, "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", "power_model": null, "sequential_access": false, "assoc": 2, "cxx_class": "LRU", "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.dcache.tags", "block_size": 64, "type": "LRU", "data_latency": 2 }, "tgts_per_mshr": 20, "demand_mshr_reserve": 1, "power_model": null, "addr_ranges": [ "0:18446744073709551615:0:0:0:0" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu.dcache", "data_latency": 2, "tag_latency": 2, "name": "dcache", "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 2 }, "isa": [ { "name": "isa", "system": "system", "eventq_index": 0, "cxx_class": "AlphaISA::ISA", "path": "system.cpu.isa", "type": "AlphaISA" } ], "tracer": { "eventq_index": 0, "path": "system.cpu.tracer", "type": "ExeTracer", "name": "tracer", "cxx_class": "Trace::ExeTracer" } } ], "intrctrl": { "name": "intrctrl", "sys": "system", "eventq_index": 0, "cxx_class": "IntrControl", "path": "system.intrctrl", "type": "IntrControl" }, "multi_thread": false, "l2": { "cpu_side": { "peer": "system.tol2bus.master[0]", "role": "SLAVE" }, "clusivity": "mostly_incl", "prefetcher": null, "system": "system", "write_buffers": 8, "response_latency": 20, "cxx_class": "Cache", "size": 2097152, "type": "Cache", "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.membus.slave[2]", "role": "MASTER" }, "mshrs": 20, "writeback_clean": false, "p_state_clk_gate_min": 1000, "tags": { "size": 2097152, "tag_latency": 20, "name": "tags", "p_state_clk_gate_min": 1000, "eventq_index": 0, "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", "power_model": null, "sequential_access": false, "assoc": 8, "cxx_class": "LRU", "p_state_clk_gate_max": 1000000000000, "path": "system.l2.tags", "block_size": 64, "type": "LRU", "data_latency": 20 }, "tgts_per_mshr": 12, "demand_mshr_reserve": 1, "power_model": null, "addr_ranges": [ "0:18446744073709551615:0:0:0:0" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.l2", "data_latency": 20, "tag_latency": 20, "name": "l2", "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 8 }, "cpu_voltage_domain": { "name": "cpu_voltage_domain", "eventq_index": 0, "voltage": [ "1.0" ], "cxx_class": "VoltageDomain", "path": "system.cpu_voltage_domain", "type": "VoltageDomain" }, "mem_ctrls": [ { "static_frontend_latency": 10000, "tRFC": 260000, "activation_limit": 4, "in_addr_map": true, "IDD3N2": "0.0", "tWTR": 7500, "IDD52": "0.0", "clk_domain": "system.clk_domain", "channels": 1, "write_buffer_size": 64, "device_bus_width": 8, "VDD": "1.5", "write_high_thresh_perc": 85, "cxx_class": "DRAMCtrl", "bank_groups_per_rank": 0, "IDD2N2": "0.0", "port": { "peer": "system.membus.master[1]", "role": "SLAVE" }, "tCCD_L": 0, "IDD2N": "0.032", "p_state_clk_gate_min": 1000, "null": false, "IDD2P1": "0.032", "eventq_index": 0, "tRRD": 6000, "tRTW": 2500, "IDD4R": "0.157", "burst_length": 8, "tRTP": 7500, "IDD4W": "0.125", "tWR": 15000, "banks_per_rank": 8, "devices_per_rank": 8, "IDD2P02": "0.0", "default_p_state": "UNDEFINED", "p_state_clk_gate_max": 1000000000000, "IDD6": "0.02", "IDD5": "0.235", "tRCD": 13750, "type": "DRAMCtrl", "IDD3P02": "0.0", "tRRD_L": 0, "IDD0": "0.055", "IDD62": "0.0", "min_writes_per_switch": 16, "mem_sched_policy": "frfcfs", "IDD02": "0.0", "IDD2P0": "0.0", "ranks_per_channel": 2, "page_policy": "open_adaptive", "IDD4W2": "0.0", "tCS": 2500, "power_model": null, "tCL": 13750, "read_buffer_size": 32, "conf_table_reported": true, "tCK": 1250, "tRAS": 35000, "tRP": 13750, "tBURST": 5000, "path": "system.mem_ctrls", "tXP": 6000, "tXS": 270000, "addr_mapping": "RoRaBaChCo", "IDD3P0": "0.0", "IDD3P1": "0.038", "IDD3N": "0.038", "name": "mem_ctrls", "tXSDLL": 0, "device_size": 536870912, "kvm_map": true, "dll": true, "tXAW": 30000, "write_low_thresh_perc": 50, "range": "0:536870911:12:19:0:0", "VDD2": "0.0", "IDD2P12": "0.0", "p_state_clk_gate_bins": 20, "tXPDLL": 0, "IDD4R2": "0.0", "device_rowbuffer_size": 1024, "static_backend_latency": 10000, "max_accesses_per_row": 16, "IDD3P12": "0.0", "tREFI": 7800000 } ], "num_work_ids": 16, "work_item_id": -1, "exit_on_work_items": false }, "time_sync_period": 100000000000, "eventq_index": 0, "time_sync_spin_threshold": 100000000, "cxx_class": "Root", "path": "root", "time_sync_enable": false, "type": "Root", "full_system": true }

Please Help

jrpdn commented 4 years ago

Hello guys, I am encountering the same error, does anyone have a solution for that?

Thanks and regards