Closed kalkyl closed 3 months ago
MANY THANKS!!!!
I had tried your example but it panicked on the first attempt to build Flash
. Could you check this PR reflects all your updates?
error message:
ERROR panicked at /Users/dicklessgreat/.cargo/git/checkouts/embassy-9312dcb0ed774b29/b88dc13/embassy-stm32/src/qspi/mod.rs:215:46:
attempt to subtract with overflow
Replaced all self.qspi.blocking_write(&[], transaction)
with self.qspi.command(transaction);
. Then it works fine but yet assertion fails.
INFO Flash UUID: [88, 50, 33, 34, 38, 33, 37, 0, c, 27, 28, ff, 1, 1, ff, ff]
└─ mytest::____embassy_main_task::{async_fn#0} @ examples/test.rs:294
ERROR panicked at 'assertion failed: read_buf == write_buf'
└─ mytest::____embassy_main_task::{async_fn#0} @ examples/test.rs:311
ERROR panicked at /Users/dicklessgreat/.cargo/registry/src/index.crates.io-6f17d22bba15001f/defmt-0.3.8/src/lib.rs:367:5:
explicit panic
└─ panic_probe::print_defmt::print @ /Users/dicklessgreat/.cargo/registry/src/index.crates.io-6f17d22bba15001f/panic-probe-0.3.2/src/lib.rs:104
Ahh, looks like more DummyCycles are needed in your case, try lowering the mul in the Pll1 back to 200 (for 400MHz) or increase the DummyCycles to 8 or so?
Also, I forgot to add that in case you set Pll1 up for 480MHz, you should also set config.rcc.voltage_scale = VoltageScale::Scale0;
in the rcc config (but that shouldn't be the issue here, i'd bet on the DummyCycles were marginal but working on my side)
config.rcc.pll1 = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL200, // 400MHz
// mul: PllMul::MUL240, // 480MHz
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV5),
divr: Some(PllDiv::DIV2),
});
and DummyCyles
8, then works fine!!!
Cool! If you boost it to 480MHz again you might need to adjust this even further
...also, boosting to 480MHz might require running FMC off of Pll2 since the official max freq is 100MHz, so perhaps leave it at 400MHz for now...
Tested 480MHz and 8 DummyCycles, then works fine. Hmm? seems pll1 clock does not matter. Data sheet says FAST_READ_QUAD_IO_CMD(or FRQIO) dummy cycles should be 6, but why does it require 8??
Yeah that's where I got my value from, but now I see other people also using 8 for this part, so maybe that's a proven value in real life. 6 worked on my board however, and I didn't have panics on the empty writes, I guess I didn't try it after bumping your embassy version to latest though
I can have a look at configuring Pll2 for FMC later if you haven't already, as is now it's working out of specs at 480MHz (so 240MHz kernel and prescaler 1 gives 120MHz instead of 100MHz)
Yeah that's where I got my value from, but now I see other people also using 8 for this part, so maybe that's a proven value in real life. 6 worked on my board however, and I didn't have panics on the empty writes, I guess I didn't try it after bumping your embassy version to latest though
Oh, my.....lol Is that possible???
I can have a look at configuring Pll2 for FMC later if you haven't already, as is now it's working out of specs at 480MHz (so 240MHz kernel and prescaler 1 gives 120MHz instead of 100MHz)
I haven't! Please go, master!!
I saw you had started on a flash implementation, here's a working version of it but provided as a minimum example you can use (didn't know how you wanted to incorporate it into your api)