Wrong PMOD JB Numbering

[floriab]

The correct numbering must be

#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; 
#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }];
#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; 
#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; 
#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; 
#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[8] }]; 
#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[9] }]; 
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[10] }]; 

wrong .xdc file in https://github.com/Digilent/Arty/blob/master/Projects/XADC_Demo/src/constraints/Arty_Master.xdc

[artvvb]

The name entered in the get_ports field is the name used internally by Vivado, and references the input and output ports of the top module of an HDL design. The physical pin location is what is used to actually route the signal to the appropriate place on the pmods port.

[artvvb]

Note that the name is just a convention and you can change it as you want in your code. The numbering scheme in the XDC file allows you to declare a port as "inout [7:0] jb;" rather than "inout [4:1]jb;" and "inout [10:7];", at least in verilog. This makes for cleaner code, though the numbering may be initially confusing (note the schematic name in comments).

[artvvb]

I have misread the issue, reopened

[floriab]

i saw the PMOD JA is also wrong (pin 10), the whole PMOD pinout shoud be checked

[artvvb]

The get_port names are not really the issue, as long as the rest of the project was written with the modified names in mind, I am concerned that the PACKAGE_PIN numbers for JB do not match the ones in the Master XDC

[floriab]

yes, i should have been there more specific, sorry