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Digilent / ZYBO

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Projects: hdmi_in: Design does not meet timing #2

Open sbobrowicz opened 8 years ago

sbobrowicz commented 8 years ago

The design does not currently meet timing due to an intra clock failure within the axi_mem_intercon core. Adding registers to the Slave interfaces should solve this issue. This was already done in the original project, but may have not been captured correctly by the Export Block Diagram tool.

sbobrowicz commented 8 years ago

Note that even though it does not meet timing, the project seems to be functional and has been tested

sbobrowicz commented 8 years ago

Adding the registers did not solve the problem. It appears the memory interconnect speed will need to be turned down from 150MHz. We might be able to get away with turning down the frequency to 140MHz and still have enough bandwidth for 1080p. The fifos in the interconnect should be enabled to 512 for all interfaces, to aid in buffering. Also the vid2axi-stream core's fifo will need to be turned up to at least 2048, maybe 4096. If we still have bandwidth issues at that point we can try adjusting the burst width of the VDMA.

Assuming that the fifo's on the input pipeline are large enough to fit an entire line, the 1080p horizontal blanking interval allows the minimum theoretical frequency of just under 130MHz.