Vivado 2019.1 - Githubissues

zyuri commented 5 years ago

Hi there,

I am trying to get the MIPI_CSI_2_RX to work in 2019.1 First of all, yes I have read the project is supposed to be used in 2018.2 and that there might be an update once a year.

I realize you guys are busy, but I would like to get a better understanding of the code.

I read here [https://www.xilinx.com/support/answers/71806.html] the axis_data_count port was removed and we should use wr_axis_data_count instead: AXI4-Stream Data FIFO (2.0)

Version 2.0
Port Change: Removed m_axis_aresetn port. The FIFO is only reset from the s_axis_aresetn pin on s_axis_aclk domain.
Port Change: Removed axis_data_count port. Use wr_axis_data_count instead.
Port Change: Status ports wr_axis_data_count, rd_axis_data_count are now optional.

Now, being a beginner at fpga, is this something I can upgrade myself? What has exactly changed to the port, was it a name change, port really removed or an even more thorough change? What should be done to upgrade?

Or should I remove lines 111 and 592 in that file and will another part of the code have to use wr_axis_data_count (should this be axis_wr_data_count??)? Where is axis_data_count actually used?

Is there a plan to upgrade to a 2019.x version of vivado?

Best regards, Yuri

Bucknalla commented 4 years ago

@zyuri did these changes fix the IP core for you?

dltemple commented 4 years ago

@zyuri @Bucknalla has anyone gotten this implemented without synthesis errors in 2019.1?

Bucknalla commented 4 years ago

@dltemple unfortunately not - I'm close but haven't had a chance yet to revisit this; ended up just using 2018.2 for the time being

zyuri commented 4 years ago

Hi, sorry for the delay... No, I switched to HDMI input, it would be nice to get this working though.

JanFortmann commented 4 years ago

Have you meanwhile found a solution to the problem? I'm working on it myself right now, but I can't find anything to upgrade the tutorial to Vivado 2019.2

natalieeliachevsky commented 4 years ago

I'm in the middle of trying to upgrade it to 2019.1. There were a couple of implementation points i had to update (in port mappings, you can't have val => not otherVal) I just added a signal to do the NOT processing then assigned that value to the port mapping.

I'm currently stuck due to multiple drivers on about 20 pins.

elodg commented 4 years ago

https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases/tag/v2019.1-1

Digilent / Zybo-Z7-20-pcam-5c

Vivado 2019.1 #11