hello,
I updated the project to Vivado 2017.2. I have a problem with synthesis though:
using the global synthesis flow fails with error message
using the OOC synthesis succeeds but does not meet timing
The synthesis error is as follows:
[DRC INBB-3] Black Box Instances: Cell 'system_i/MIPI_CSI_2_RX_0/U0' of type 'system_i/MIPI_CSI_2_RX_0/U0/mipi_csi2_rx_top' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
The same error message was observed in 2016.4 too. Could not find a reasonable explanation to it and the workaround was to re-create the project from sources.
hello, I updated the project to Vivado 2017.2. I have a problem with synthesis though:
The synthesis error is as follows: [DRC INBB-3] Black Box Instances: Cell 'system_i/MIPI_CSI_2_RX_0/U0' of type 'system_i/MIPI_CSI_2_RX_0/U0/mipi_csi2_rx_top' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
does this happen with 2016.4 as well?