Digilent / Zybo-hdmi-out

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project showing errors in vivado 2018.3 #1

Open Arvint89 opened 5 years ago

Arvint89 commented 5 years ago

Hi, I am new to fpga based design and I am trying to do this tutorial and understand it. But it is not working on my system. I have errors 1 error in block design and 6 in implementation.

Block design error [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'hdmi_out.bd' is locked. Locked reason(s):

do I need to unlock IP to make it work? how do I do that?

I think if I fix this implementation errors might get solved. But either way I am posting the place and route errors [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: HDMI_DDC_scl_io Term: HDMI_DDC_sda_io Term: IIC_0_scl_io Term: and IIC_0_sda_i [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances

ashtonchase commented 5 years ago

I believe you need to update the IP cores in the block design. I was able to do with without issue in 2018.2 With the block design open, from the toolbar Navigate to Reports->Report IP Status. The IP Status dialog will appear, you need to select all of them and select the Update Selected button.

Hope this helps.

rishubn commented 3 years ago

@ashtonchase I am having this issue with 2021.1 and after having upgrading the IPs

jung-youjin commented 3 years ago

@rishubn Hi, have you solved this issue?