Closed bbardi closed 4 years ago
This pull request adds support for capturing synthesis and implementation settings that differ from Vivado defaults and fixed support for Block Designs with IPs that create their own BD such as Xilinx's MIPI CSI-2 Rx Subsystem.
I cherry picked defaults-fix instead of using the merge commit, and fast forwarded v2020.1, in order to preserve some semblance of linear history.
This pull request adds support for capturing synthesis and implementation settings that differ from Vivado defaults and fixed support for Block Designs with IPs that create their own BD such as Xilinx's MIPI CSI-2 Rx Subsystem.