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Digilent / digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.
MIT License
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RX/TX IN/OUT in interface names mixed #2

Closed DanielKOcean closed 7 years ago

DanielKOcean commented 7 years ago

Receive port must be named as input and transmit port must be named as output.

Now:

set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uartrxdout }]; #IO_25_14 Sch=uartrxdout

set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uarttxdin }]; #IO_L24N_T3_A00_D16_14 Sch=uarttxdin

Correct:

set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uartrxdin }]; #IO_25_14 Sch=uartrxdin

set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uarttxdout }]; #IO_L24N_T3_A00_D16_14 Sch=uarttxdout