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Digilent / digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.
MIT License
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DDR pin #9

Open LeiWang1999 opened 5 years ago

LeiWang1999 commented 5 years ago

Why such as nexys4-ddr xdc file doesn't have ddr pin . how can i use it?

LeiWang1999 commented 5 years ago

then. a few months later, i should give an anser. this ddr2 control is very hard, because a great amount of vivado project or any other eda software project use ddr3 or ddr . so to use it ,you should use a core like microblaze or zynq . and with a ipcore which named "mig" and also to auto config it , use board file . then ,ok

Hyalliti commented 5 years ago

Thanks for posting a follow up. It's pretty useful to consider it now when buying a zynq for 129usd or less...

someone755 commented 2 years ago

Apologies for the necropost. At least for the S7-50 there is a way to extract the basic constraints (pin name, iostandard, slew rate) for the DDR3 I/Os from the .UCF file supplied by Digilent for use with the MIG core.

Even better, after configuring the MIG core with said UCF file, one of the files the IP generates is an .XDC constraints file from which you can directly copy the entries into your project if you require exclusive control of these pins (outside of the MIG IP). Maybe this advice will help somebody in the future.

The issue I'm having now, however, is that I cannot find any timing constraints for these pins. I'm working with an Arty S7-50 board but I can't seem to find the trace lengths that I would need to make an educated guess as to the proper input delays.