search

Digilent / vivado-library

MIT License
564 stars 309 forks source link

IP error for PmodSD and PmodWIFI when adding the repo path to catalog #8

Closed elodg closed 7 years ago

elodg commented 7 years ago

WARNING: [IP_Flow 19-395] Problem reading Component: see 'xilinx:coreExtensions' near line 0 in d:/vivado-library/ip/Pmods/PmodSD_v1_0/component.xml: Bad end of element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file d:/vivado-library/ip/Pmods/PmodSD_v1_0/component.xml. This IP will not be included in the IP Catalog. WARNING: [IP_Flow 19-395] Problem reading Component: see 'xilinx:coreExtensions' near line 0 in d:/vivado-library/ip/Pmods/PmodWIFI_v1_0/component.xml: Bad end of element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file d:/vivado-library/ip/Pmods/PmodWIFI_v1_0/component.xml. This IP will not be included in the IP Catalog.

elodg commented 7 years ago

There is an incompatibility between IPs generated in 2016.x when loaded in 2015.x. I recommend re-packaging the two IPs with the error in 2015.x versions.

michael1888 commented 7 years ago

how to " re-packaging the two IPs " in 2015.x ? Would you mind elaborating a bit more details? Thanks in advance.

elodg commented 7 years ago

There is an incompatibility between the component.xml generated by 2016.x versions and Vivado 2015.x loading repositories with those xmls. I could not track down exactly which part is causing issues. One could re-package the IPs in 2015.x by creating a new IP definition, importing the source files and replicating the wizard settings present in the 2016.x IP version.

michael1888 commented 7 years ago

Hi elodge,

Just notice there are vhdl source files in this package, /vivado-library-master/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com, which contains directory axi_gpio_v2_0, axi_lite_ipif_v3_0, ax_quad_spi_v3_2 etc. Can I just group the necessary source files together in vivado 2015.x to build my own IP?

Also curiously, the reference directories are modified, i.e., axi_gpio_v2_0_11 instead of axi_gpio_v2_0; ax_quad_spi_v3_2_8 instead of axi_gpio_v2_0 etc. Also inside source files, instantiation uses other name, i.e., axi_gpio_0 instead of axi_gpio, axi_quad_spi_0 instead of axi_quad_spi. All these details cost other designer much efforts to get things straight.

Your thoughts and suggestions are always highly appreciated, thanks in advance.

elodg commented 7 years ago

Those are generated files for Xilinx IP packaged inside our IP. Looking at the IP definition I don't think ipshared should be there at all because only the customization files (xci) are added as sources. Any other files are generated by Vivado when the IP is instantiated. You could add the vhdl or even netlist instead but you will lose upgrade functionality. When upgrading to new Vivado versions, sub-IPs added as xci are upgraded automatically.

michael1888 commented 7 years ago

Hi elodge,

/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/ blk_mem_gen_v8_3 , dist_mem_gen_v8_0, fifo_generator_v13_1 are in protected mode. vivado complains of adding them into a project.

Let's focus on your previous suggestion, " 2015.x creating a new IP definition, importing the source files and replicating 2016.x wizard settings ", please inform where the source files are located, thanks in advance.

elodg commented 7 years ago

Instantiate the IP in a block design, right click an choose Edit in IP Packager. You will be able to see all the source files and wizard GUI customizations. You need to make the new IP look and behave the same. Looking at the source files, it is mostly a wrapper for other IP. @tom21091 should know more about this than I do.

michael1888 commented 7 years ago

I migrate to latest version of Xilinx tools. Sorry for the trouble. Thanks for suggestions.