The code did not work in cadence. Some of the code was not explict enough and cadence flags a exceptions of a increment rolls over its maximum, in fpga land this is modulo, so that is what the code has been changed to.
This code has been verified in simulation and synthesis.
The code did not work in cadence. Some of the code was not explict enough and cadence flags a exceptions of a increment rolls over its maximum, in fpga land this is modulo, so that is what the code has been changed to.
This code has been verified in simulation and synthesis.