Closed JamiKettunen closed 9 months ago
Hello, can you please download and compile the last fix in bugfix4
branch and report the output of ./cpufetch -v
?
$ ./cpufetch -v
[WARNING]: Not parsed multi-letter extension: zicntr
[WARNING]: Not parsed multi-letter extension: zicsr
[WARNING]: Not parsed multi-letter extension: zifencei
[WARNING]: Not parsed multi-letter extension: zihpm
[WARNING]: Not parsed multi-letter extension: zba
[WARNING]: Not parsed multi-letter extension: zbb
#######
################.
############ ###########
############ ##########.
############ # ###### SoC: StarFive VisionFive 2
########### ##### ## Technology: 28nm
#######. ########## Microarchitecture: U74
###### ### *########### Cores: 4 cores
###### #######. ########## Max Frequency: 1.500 GHz
######### ############ ###### Extensions: rv64imafdc_zicntr_zicsr_zifencei_zihpm_zba_zbb
###########. ###########* # - (I) Integer Instruction Set
############ ############ - (M) Integer Multiplication and Division
# ############. .########### - (A) Atomic Instructions
###### ########### ######### - (F) Single-Precision Floating-Point
########## .######, ##### - (D) Double-Precision Floating-Point
############ ##. #####. - (C) Compressed Instructions
######### ######## Peak Performance: 6.00 GFLOP/s
## ##### ##########.
####### # ############
########### ###########.
###########. ############
################
The fix appears to work, did you have something more in mind to do with the multi-letter extensions still?
Hello, I have added a few more patches and now it should work properly. Can you please confirm in your end?
Looks about right
#######
################. SoC: StarFive VisionFive 2
############ ########### Technology: 28nm
############ ##########. Microarchitecture: U74
############ # ###### Cores: 4 cores
########### ##### ## Max Frequency: 1.500 GHz
#######. ########## Extensions: rv64imafdc_zicntr_zicsr_zifencei_zihpm_zba_zbb
###### ### *########### - (I) Integer Instruction Set
###### #######. ########## - (M) Integer Multiplication and Division
######### ############ ###### - (A) Atomic Instructions
###########. ###########* # - (F) Single-Precision Floating-Point
############ ############ - (D) Double-Precision Floating-Point
# ############. .########### - (C) Compressed Instructions
###### ########### ######### - (Zbb) Basic bit-manipulation
########## .######, ##### - (Zba) Address Generation
############ ##. #####. - (Zicntr) Base Counters and Timers
######### ######## - (Zicsr) Control and Status Register
## ##### ##########. - (Zifencei) Instruction-Fetch Fence
####### # ############ - (Zihpm) Hardware Performance Counters
########### ###########. Peak Performance: 6.00 GFLOP/s
###########. ############
################
LGTM. I'll merge this into main, thanks for reporting the issue!
I see the titled error when running
./cpufetch
after build on my VisionFive 2 (JH7110 SoC) with https://chimera-linux.org/:The command still appears to mostly work and exists with code 0, and it doesn't appear to be present if I try
./cpufetch --logo-short
instead:My theory is it tries to address the hypervisor core in the
--logo-long
mode as it also printsSupervisor-level Instructions
under extensions before erroring; my kernel is v6.5 from https://github.com/esmil/linux/tree/jh7110/ with mainline U-Boot & OpenSBI as well