Open sammary114 opened 3 months ago
Hi, thanks for your report. I've pushed a fix into a new branch called i259
, can you confirm if it works as expected?
oh, its Soc
and Technology
is UnKnown
, Microarchitecture
is normal.
~/cpufetch $ ./cpufetch --verbose
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
[WARNING]: SoC detection failed using Android property ro.board.platform: kirin9000s
[WARNING]: SoC detection failed using Android: Found 'kirin9000s' string
[WARNING]: read_file: /sys/bus/nvmem/devices/rockchip-efuse0/nvmem: No such file or directory
[WARNING]: read_file: /sys/bus/nvmem/devices/rockchip-otp0/nvmem: No such file or directory
[WARNING]: guess_soc_from_uarch: No uarch matched the list
opendir: Permission denied
[WARNING]: guess_soc_from_pci: Unable to find suitable PCI devices
SoC: Unknown
Technology: Unknown
CPU 1:
Microarchitecture: Cortex‑A510
Max Frequency: 1.530 GHz
Cores: 4 cores
##### ## # ##### ## #### ###### Features: NEON,SHA1,SHA2,AES,CRC32
### #### ### #### ### ### CPU 2:
### ## ### ### ## ### Microarchitecture: TaiShan v120
### #### ### ### ## ### Max Frequency: 2.150 GHz
###### ## ### ### ## ### Cores: 3 cores
Features: NEON,SHA1,SHA2,AES,CRC32
CPU 3:
Microarchitecture: TaiShan v120
Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SHA1,SHA2,AES,CRC32
Peak Performance: 85.24 GFLOP/s
~/cpufetch $ ./cpufetch --debug
opendir: Permission denied
cpufetch v1.05-30-g483f (Android ARM build)
[Core 0] 0x411FD461 1530 MHz
[Core 1] 0x411FD461 1530 MHz
[Core 2] 0x411FD461 1530 MHz
[Core 3] 0x411FD461 1530 MHz
[Core 4] 0x482FD422 2150 MHz
[Core 5] 0x482FD422 2150 MHz
[Core 6] 0x482FD422 2150 MHz
[Core 7] 0x482FD022 2620 MHz
~/cpufetch $
My bad, could you try again with the new patch I just pushed?
Commit: 3e3a42f1
The make
is output:
~/cpufetch $ make
cc -Wall -Wextra -pedantic -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all -O2 -Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes -DGIT_FULL_VERSION=\""v1.05-31-g3e3a"\" src/common/main.c src/common/cpu.c src/common/udev.c src/common/printer.c src/common/args.c src/common/global.c src/common/freq.c src/arm/midr.c src/arm/uarch.c src/common/soc.c src/arm/soc.c src/common/pci.c src/arm/udev.c -o cpufetch
src/arm/soc.c:177:10: warning: variable 'tmp' is uninitialized when used here [-Wuninitialized]
177 | SOC_EQ(tmp, "hi3620GFC", "K3V2", SOC_HISILICON_3620, soc, 40)
| ^~~
src/arm/../common/soc.h:53:28: note: expanded from macro 'SOC_EQ'
53 | else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
| ^~~~~~~~
src/arm/soc.c:172:12: note: initialize the variable 'tmp' to silence this warning
172 | char* tmp;
| ^
| = NULL
1 warning generated.
The commit 3e3a42f1
's cpufetch
is output:
~/cpufetch $ ./cpufetch --verbose
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
SoC: Unknown
Technology: Unknown
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: 6 NEON,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SHA1,SHA2,AES,CRC32
Peak Performance: 85.24 GFLOP/s
~/cpufetch $
CpuLogo is display, but Soc
and Technology
is UnKnown
My bad (again), new patch, can you give it a try?
All right, the output is seems normal:
~/cpufetch $ rm cpufetch
~/cpufetch $ make
cc -Wall -Wextra -pedantic -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all -O2 -Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes -DGIT_FULL_VERSION=\""v1.05-32-g93d5"\" src/common/main.c src/common/cpu.c src/common/udev.c src/common/printer.c src/common/args.c src/common/global.c src/common/freq.c src/arm/midr.c src/arm/uarch.c src/common/soc.c src/arm/soc.c src/common/pci.c src/arm/udev.c -o cpufetch
~/cpufetch $ ./cpufetch --verbose
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SHA1,SHA2,AES,CRC32
Peak Performance: 85.24 GFLOP/s
~/cpufetch $
Need me to close issues?
Great! One thing I noticed is the peak performance which is incorrect. I have fixed this and also pushed a test to check if your CPU supports SVE. Could you give it a try again?
All right, The cpufetch
is output:
~/cpufetch $ ./cpufetch --verbose
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SHA1,SHA2,AES,CRC32
Peak Performance: 194.08 GFLOP/s
SVE: Yes
SVE2: No
[4] SVE vector length is: 16 bytes
[7] SVE vector length is: 16 bytes
[0] SVE vector length is: 16 bytes
Wow, that's great! Your CPU has SVE which is not very common nowadays.
I have pushed a new patch that should work in your device and show you under Features
that it supports SVE, could you please give it a last try? After that I will merge this into master and close the issue.
The log output is abnormal, because Peak Performance: 0.00 MFLOP/s
:
~/cpufetch $ ./cpufetch --verbose
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SVE,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SVE,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SVE,SHA1,SHA2,AES,CRC32
Peak Performance: 0.00 MFLOP/s
~/cpufetch $ ./cpufetch --debug
cpufetch v1.05-35-g26af (Android ARM build)
[Core 0] 0x411FD461 1530 MHz
[Core 1] 0x411FD461 1530 MHz
[Core 2] 0x411FD461 1530 MHz
[Core 3] 0x411FD461 1530 MHz
[Core 4] 0x482FD422 2150 MHz
[Core 5] 0x482FD422 2150 MHz
[Core 6] 0x482FD422 2150 MHz
[Core 7] 0x482FD022 2620 MHz
~/cpufetch $
Wow, that's great! Your CPU has SVE which is not very common nowadays.
I have pushed a new patch that should work in your device and show you under
Features
that it supports SVE, could you please give it a last try? After that I will merge this into master and close the issue.
The cpu's taishan v120
architecture supports hyper-threading. Does it affect Peak Performance?
My bad (again), it's a bit tricky to implement SVE detection. I have pushed a new patch, this should be the final one, can you please confirm if it works as expected? Thanks so much for the feedback!
Wow, that's great! Your CPU has SVE which is not very common nowadays. I have pushed a new patch that should work in your device and show you under
Features
that it supports SVE, could you please give it a last try? After that I will merge this into master and close the issue.The cpu's
taishan v120
architecture supports hyper-threading. Does it affect Peak Performance?
Hyperthreading does not affect peak performance. Still, cpufetch should report that your CPU supports hyperthreading, but it's not doing that at the moment. It seems like your Linux kernel is not properly reporting that your CPU has hyperthreading, which seems weird. It's possible that cpufetch is not properly interpreting the data, I will definitely have a look at this.
The output is here:
~/cpufetch $ make
cc: error: no such file or directory: 'foo.c'
cc: error: no input files
cc -Wall -Wextra -pedantic -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all -march=armv8-a+sve -O2 -Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes -DGIT_FULL_VERSION=\""v1.05-36-gf6cd"\" src/common/main.c src/common/cpu.c src/common/udev.c src/common/printer.c src/common/args.c src/common/global.c src/common/freq.c src/arm/midr.c src/arm/uarch.c src/common/soc.c src/arm/soc.c src/common/pci.c src/arm/udev.c -o cpufetch
src/arm/midr.c:150:17: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
150 | : "=r"(x0));
| ^
src/arm/midr.c:149:26: note: use constraint modifier "w"
149 | __asm volatile("cntb %0"
| ^~
| %w0
1 warning generated.
~/cpufetch $ ./cpufetch --debug
cntb=16
cntb=16
cntb=16
cpufetch v1.05-36-gf6cd (Android ARM build)
[Core 0] 0x411FD461 1530 MHz
[Core 1] 0x411FD461 1530 MHz
[Core 2] 0x411FD461 1530 MHz
[Core 3] 0x411FD461 1530 MHz
[Core 4] 0x482FD422 2150 MHz
[Core 5] 0x482FD422 2150 MHz
[Core 6] 0x482FD422 2150 MHz
[Core 7] 0x482FD022 2620 MHz
~/cpufetch $ ./cpufetch --verbose
cntb=16
cntb=16
cntb=16
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SVE,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SVE,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SVE,SHA1,SHA2,AES,CRC32
Peak Performance: 194.08 GFLOP/s
Sorry for the large amount of testing. I have pushed one last commit to the branch. It should finally work with no warning and no weird issues. If it doesn't I will just merge support for your CPU into master and I will leave the SVE detection feature for another time.
Thank your for your feedback :+1:
Ok, The make
output is seems normal:
~/cpufetch $ make
cc -Wall -Wextra -pedantic -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all -O2 -Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes -DGIT_FULL_VERSION=\""v1.05-38-gd2bd"\" src/common/main.c src/common/cpu.c src/common/udev.c src/common/printer.c src/common/args.c src/common/global.c src/common/freq.c src/arm/midr.c src/arm/uarch.c src/common/soc.c src/arm/soc.c src/common/pci.c src/arm/udev.c sve.o -o cpufetch
~/cpufetch $ ./cpufetch --verbose
cntb=16
cntb=16
cntb=16
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SVE,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SVE,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SVE,SHA1,SHA2,AES,CRC32
Peak Performance: 194.08 GFLOP/s
Nice! I've merged support for your SoC and SVE detection into master :+1:
Just a small note: cpu4
- cpu6
have a different identifier compared to cpu7
(d42
vs. d02
).
Historically the d4
range was used for Cortex derivates by HiSilicon (starting with A76/d40
) while their own cores were in the d0
range.
Just a small note:
cpu4
-cpu6
have a different identifier compared tocpu7
(d42
vs.d02
).Historically the
d4
range was used for Cortex derivates by HiSilicon (starting with A76/d40
) while their own cores were in thed0
range.
That's a very good point. cpu7
is clearly TaiShan v120
, but cores cpu4
-cpu6
are not clear to me. As you said, it is well known that d40
is Cortex A76 but I cannot find the exact microarchitecture for d42
online. If you have any relevant information about this please feel free to share it. Also, could be helpful if @sammary114 would post a screenshot of CPU-Z.
Another concerning topic is hyper-threading. In this case, the Linux kernel does not seem to be reporting hyper-threading (in /proc/cpuinfo it only shows the 8 physical cores). However, I wonder if hyper-threading is only available in the 12-core and not on the 8-core SoCs? I cannot find relevant information about this either...
Re-opening to give this more visibility and potentially adding more commits in the future.
Sorry for the large amount of testing. I have pushed one last commit to the branch. It should finally work with no warning and no weird issues. If it doesn't I will just merge support for your CPU into master and I will leave the SVE detection feature for another time.
Thank your for your feedback 👍
When I run cat /sys/devices/system/cpu/smt/active
in Termux, is output 1
I wonder if hyper-threading is only available in the 12-core and not on the 8-core SoCs?
I wonder whether the '12-core" SoCs are not simply those with SMT enabled. If we search for "part 3330" in Geekbench Browser ('part 3330' translates to 0xd02
in Geekbench speech -> the string 'ARM implementer 72 architecture 8 variant 2 part 3330 revision 2' translates to 'Taishan v120 (48/d02) r2p2') then in the middle of the first page we see two results for something called HUAWEI TGR-W10 from Aug 15th right now: https://browser.geekbench.com/search?utf8=✓&q=%22part+3330%22
The '12-core variant' performs marginally better in the multicore score and the cluster layout is as follows:
By looking at Geekbench's collected metadata these relevant parts are the same so I would assume that's the same device one time with SMT enabled and the other not: https://browser.geekbench.com/v6/cpu/7344311.gb6 vs. https://browser.geekbench.com/v6/cpu/7344235.gb6
{
"id": 29,
"value": "7.62 GB",
"ivalue": 8182185984
},
{
"id": 34,
"value": "Maleoon 910",
"ivalue": 0
},
{
"id": 41,
"value": "TGR-W10G 4.2.0.158(C00E155R2P5)",
"ivalue": 0
},
{
"id": 90,
"value": "Linux 5.10.43 aarch64",
"ivalue": 0
},
Edit: last Dec a 3rd cluster variant with at least two Taishan v120 r2p2 appeared on Geekbench Browser: https://browser.geekbench.com/search?page=4&q=ADA-AL00U
Cluster layout as follows: 3 Cores @ 1.53 GHz, 4 Cores @ 2.15 GHz, 2 Cores @ 2.35 GHz
Geekbench 6 on Linux and Android builds the cluster info running ascending through cpu0
to cpuN
(though not sure whether based on cpufreq info or core type)
Edit 2: the '9-core variant' appearing on Geekbench seems to be the 9000SL with SMT enabled (so in reality it's a 3+2+1 cluster layout). The (rather low) GB6 scores hint in this direction too.
Edit 3: Geekbench differentiates clusters by cpufreq metadata: This here is something with eight Cortex-A53, four of them limited to 1.0 GHz, the other to 1.4 GHz (Amlogic faking the frequency to be shown as 1.5 GHz).
Also, could be helpful if @sammary114 would post a screenshot of CPU-Z.
I second this :)
Also, could be helpful if @sammary114 would post a screenshot of CPU-Z.
Strange that CPU-Z shows a different picture compared to /proc/cpuinfo
. Maybe there's something dynamic going on and SMT gets enabled/disabled 'on demand' and the proc
driver hides the virtual SMT cores when SMT is off? Maybe when immediately checking sysfs
and proc
they're in sync?
cat /sys/devices/system/cpu/smt/active ; cat /proc/cpuinfo
Wow, the CPU-Z screenshot has me shocked...
@sammary114 if you don't mind helping here, I would also try running ls /sys/devices/system/cpu/
. I'm curious to see how many CPUs show in that directory. Another helpful thing could be to see the contents of build.prop
. Maybe that contains some hint...
~ $ ls /sys/devices/system/cpu/ -alp
total 0
drwxr-xr-x 22 root root 0 Aug 12 15:38 ./
drwxr-xr-x 8 root root 0 Aug 12 15:38 ../
-r--r--r-- 1 root root 4096 Aug 17 14:33 aarch32_el0
drwxr-xr-x 5 root root 0 Aug 12 15:38 core_ctl/
drwxr-xr-x 7 root root 0 Aug 17 14:23 cpu0/
drwxr-xr-x 7 root root 0 Aug 17 14:23 cpu1/
drwxr-xr-x 7 root root 0 Aug 17 14:23 cpu2/
drwxr-xr-x 7 root root 0 Aug 17 14:23 cpu3/
drwxr-xr-x 8 root root 0 Aug 17 14:23 cpu4/
drwxr-xr-x 8 root root 0 Aug 17 14:23 cpu5/
drwxr-xr-x 8 root root 0 Aug 17 14:23 cpu6/
drwxr-xr-x 8 root root 0 Aug 17 14:23 cpu7/
drwxr-xr-x 5 root root 0 Aug 12 15:38 cpufreq/
drwxr-xr-x 2 root root 0 Aug 12 15:38 cpuidle/
drwxr-xr-x 2 root root 0 Aug 17 14:33 hotplug/
-r--r--r-- 1 root root 4096 Aug 17 14:33 isolated
-r--r--r-- 1 root root 4096 Aug 17 14:33 kernel_max
drwxr-xr-x 5 root root 0 Aug 17 14:33 mips_mem/
-r--r--r-- 1 root root 4096 Aug 17 14:33 modalias
-r--r--r-- 1 root root 4096 Aug 17 14:33 offline
-r--r--r-- 1 root root 4096 Aug 17 14:23 online
-r--r--r-- 1 root root 4096 Aug 17 14:32 possible
drwxr-xr-x 2 root root 0 Aug 17 14:33 power/
-r--r--r-- 1 root root 4096 Aug 16 02:17 present
drwxr-xr-x 2 root root 0 Aug 17 14:33 smt/
-rw-r--r-- 1 root root 4096 Aug 17 14:33 uevent
drwxr-xr-x 2 root root 0 Aug 17 14:33 vulnerabilities/
but the command is not display cpu
8-11, termux
app may not have permission
When I type adb shell ls
, I edit the comment.
@ThomasKaiser Regarding the microarchitecture discussion it is still unclear to me what is the right microarchitecture for d42
. About SMT, it makes sense what you suggested. I think in this case we are looking at a 4+3+1=8 which SMT are only supported in the last 2 clusters, so that would give us 4+32+12=12.
@sammary114 One last request from my side is running the getprop
command. Please be aware that this might contain some "sensitive" information about your device so feel free to either remove some fields you do not want to share or even not share it at all. But I find it promising because I suspect this could contain some field talking about SMT that could be what CPU-Z is using.
I personally think we should not overlook the following possibility: CPU-Z might be seeing the Taishan v120
and /sys/devices/system/cpu/smt/active
and could have a hardcoded rule that assumes the last two clusters have SMT enabled, even when the kernel itself does not report such. That's the only explanation I have at the moment for this.
@sammary114 One last request from my side is running the getprop command. Please be aware that this might contain some "sensitive" information about your device so feel free to either remove some fields you do not want to share or even not share it at all. But I find it promising because I suspect this could contain some field talking about SMT that could be what CPU-Z is using.
share getprop
output link:
google drive
@sammary114 Thank you so much for the feedback. Unfortunately I don't see anything to infer the SMT. Unless we are missing something I just think there is not enough evidence for a userspace program to say that this CPU supports SMT. I believe CPU-Z is trying to be too smart here.
I've edited the title and added the help wanted label hoping to attract some help to investigate this further.
@sammary114 could you run cat /sys/devices/system/cpu/cpu*/topology/thread_siblings_list
? If SMT is enabled that should give us some idea.
@sammary114 could you run
cat /sys/devices/system/cpu/cpu*/topology/thread_siblings_list
? If SMT is enabled that should give us some idea.
~ $ cat /sys/devices/system/cpu/cpu*/topology/thread_siblings_list
0
1
2
3
4-5
4-5
6-7
6-7
~ $ cat /sys/devices/system/cpu/cpu11/topology/thread_siblings_list
10-11
I do not know why the terminal does not display the CPU's 8-11
, when ls cpu
is output:
~ $ ls /sys/devices/system/cpu/cpu*
/sys/devices/system/cpu/cpu0:
core_ctl cpufreq hotplug node1 online regs topology
cpu_capacity cpuidle mips_mem of_node power subsystem uevent
/sys/devices/system/cpu/cpu1:
cpu_capacity cpuidle mips_mem of_node power subsystem uevent
cpufreq hotplug node1 online regs topology
/sys/devices/system/cpu/cpu2:
cpu_capacity cpuidle mips_mem of_node power subsystem uevent
cpufreq hotplug node1 online regs topology
/sys/devices/system/cpu/cpu3:
cpu_capacity cpuidle mips_mem of_node power subsystem uevent
cpufreq hotplug node1 online regs topology
/sys/devices/system/cpu/cpu4:
core_ctl cpufreq hotplug node1 online regs subsystem uevent
cpu_capacity cpuidle mips_mem of_node power smt topology
/sys/devices/system/cpu/cpu5:
cpu_capacity cpuidle mips_mem of_node power smt topology
cpufreq hotplug node1 online regs subsystem uevent
/sys/devices/system/cpu/cpu6:
cpu_capacity cpuidle mips_mem of_node power smt topology
cpufreq hotplug node1 online regs subsystem uevent
/sys/devices/system/cpu/cpu7:
cpu_capacity cpuidle mips_mem of_node power smt topology
cpufreq hotplug node1 online regs subsystem uevent
/sys/devices/system/cpu/cpufreq:
policy0 policy1 policy2
/sys/devices/system/cpu/cpuidle:
available_governors current_driver current_governor current_governor_ro lp_mode
But the CPU 8-11 does exist
Promising but confusing :smile:
But the CPU 8-11 does exist
What do you mean? You mean the files
/sys/devices/system/cpu/cpu8/topology/thread_siblings_list
/sys/devices/system/cpu/cpu9/topology/thread_siblings_list
/sys/devices/system/cpu/cpu10/topology/thread_siblings_list
/sys/devices/system/cpu/cpu11/topology/thread_siblings_list
exist? But it does not show up when you do ls /sys/devices/system/cpu/
though. So the files exist but they do not show when you type ls
, is that it?
For example can you do cat /sys/devices/system/cpu/cpu8/topology/thread_siblings_list
?
Promising but confusing :smile:
But the CPU 8-11 does exist
What do you mean? You mean the files
/sys/devices/system/cpu/cpu8/topology/thread_siblings_list /sys/devices/system/cpu/cpu9/topology/thread_siblings_list /sys/devices/system/cpu/cpu10/topology/thread_siblings_list /sys/devices/system/cpu/cpu11/topology/thread_siblings_list
exist? But it does not show up when you do
ls /sys/devices/system/cpu/
though. So the files exist but they do not show when you typels
, is that it?For example can you do
cat /sys/devices/system/cpu/cpu8/topology/thread_siblings_list
?
yes
~ $ cat /sys/devices/system/cpu/cpu8/topology/thread_siblings_list
8-9
~ $ cat /sys/devices/system/cpu/cpu9/topology/thread_siblings_list
8-9
~ $ cat /sys/devices/system/cpu/cpu10/topology/thread_siblings_list
10-11
~ $ cat /sys/devices/system/cpu/cpu11/topology/thread_siblings_list
10-11
I have pushed a quick test into branch i259
which will try to read all the files in the range /sys/devices/system/cpu/cpu0-11/topology/thread_siblings_list
. Can you confirm if this works? I think it would be worth to run this multiple times (for example, 10 times) to make sure that the program always find the files. If this is the case, I wonder why ls does not find them...
~/cpufetch $ ./cpufetch --verbose
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list: 0
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list: 1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list: 2
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list: 3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list: 4-5
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list: 4-5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list: 6-7
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list: 6-7
/sys/devices/system/cpu/cpu8/topology/thread_siblings_list: 8-9
/sys/devices/system/cpu/cpu9/topology/thread_siblings_list: 8-9
/sys/devices/system/cpu/cpu10/topology/thread_siblings_list: 10-11
/sys/devices/system/cpu/cpu11/topology/thread_siblings_list: 10-11
cntb=16
cntb=16
cntb=16
[WARNING]: SoC detection failed using /proc/cpuinfo: No string found
[WARNING]: SoC detection failed using Android property ro.soc.model: Kirin
[WARNING]: SoC detection failed using Android property ro.product.board: ALN
SoC: Kirin 9000s
Technology: 7nm
CPU 1:
####### Microarchitecture: Cortex‑A510
##### #################### Max Frequency: 1.530 GHz
###################################### Cores: 4 cores
####################################### Features: NEON,SVE,SHA1,SHA2,AES,CRC32
####################################### CPU 2:
############################## Microarchitecture: TaiShan v120
########################## Max Frequency: 2.150 GHz
######################### Cores: 3 cores
######################## Features: NEON,SVE,SHA1,SHA2,AES,CRC32
######################## CPU 3:
######################### Microarchitecture: TaiShan v120
######################### Max Frequency: 2.620 GHz
Cores: 1 cores
Features: NEON,SVE,SHA1,SHA2,AES,CRC32
Peak Performance: 194.08 GFLOP/s
~/cpufetch $ ./cpufetch --debug
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list: 0
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list: 1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list: 2
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list: 3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list: 4-5
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list: 4-5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list: 6-7
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list: 6-7
/sys/devices/system/cpu/cpu8/topology/thread_siblings_list: 8-9
/sys/devices/system/cpu/cpu9/topology/thread_siblings_list: 8-9
/sys/devices/system/cpu/cpu10/topology/thread_siblings_list: 10-11
/sys/devices/system/cpu/cpu11/topology/thread_siblings_list: 10-11
cntb=16
cntb=16
cntb=16
cpufetch v1.05-39-ga48e (Android ARM build)
[Core 0] 0x411FD461 1530 MHz
[Core 1] 0x411FD461 1530 MHz
[Core 2] 0x411FD461 1530 MHz
[Core 3] 0x411FD461 1530 MHz
[Core 4] 0x482FD422 2150 MHz
[Core 5] 0x482FD422 2150 MHz
[Core 6] 0x482FD422 2150 MHz
[Core 7] 0x482FD022 2620 MHz
I'm excited, but even more confused! What is the output of cat /sys/devices/system/cpu/present
!?
If it's 0-7
then the kernel is doing seriously weird and if it's 0-11
I don't know why cpufetch
is not reporting an error...
~ $ cat /sys/devices/system/cpu/present
0-7
Does termux not show the number of cpu threads after hyper-thread?
I need to investigate this deeper, but my current impression is that the kernel is tampered. As far as I understand if present
says there are N
cores, it is not legal to find /sys/devices/system/cpu/cpuX
where X > N
.
please support my device, thanks.
The output of
cpufetch --verbose
cat /proc/cpuinfo
:processor : 1 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd46 CPU revision : 1
processor : 2 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd46 CPU revision : 1
processor : 3 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd46 CPU revision : 1
processor : 4 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x48 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd42 CPU revision : 2
processor : 5 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x48 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd42 CPU revision : 2
processor : 6 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x48 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd42 CPU revision : 2
processor : 7 BogoMIPS : 3.84 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit ilrcpc flagm ssbs sb pacg dcpodp flagm2 frint svei8mm i8mm bti CPU implementer : 0x48 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd02 CPU revision : 2