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DynamoRIO / dynamorio

Dynamic Instrumentation Tool Platform
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add extra decoding entries to get the "proper" opcode names for width or reg-reg variants? #1307

Open derekbruening opened 9 years ago

derekbruening commented 9 years ago

From bruen...@google.com on November 01, 2013 10:56:41

There are a number of opcodes whose mnemonic name changes based on bitwidth or on whether reg-reg or not: see the sequence in instr.h from OP_cbw through OP_vmovlhps. These are more substantially different than the condition code variants: "jae" vs "jnb" doesn't matter much, while "pinsrd" vs "pinsrq" does matter a litle as it tells you the size of the argment, which is hard to determine with DR's default disassembly if it's a memory operand. We could add extra entries that split on modrm or on rex.w or on the data size prefix in order to have the right name, but it's not clear it's worthwhile.

Original issue: http://code.google.com/p/dynamorio/issues/detail?id=1307

derekbruening commented 9 years ago

From bruen...@google.com on November 01, 2013 07:59:11

Also note that someone using our #define of OP_pinsrq may not be happy that we allow an operand size that would only go with OP_pinsrd.

derekbruening commented 1 year ago

There doesn't seem to be a separate issue on adding first-class support for disassembly in conventional assembler styles like Intel and AT&T for x86: xref #1683 for that on AArch32. Generally we've thought about adding printf templates to each decode table entry -- but we would still need to split entries up as noted in this issue.