Add fast-forward feature to skip N instructions in drmemtrace analysis tools

[derekbruening]

This is a feature request to make it easier to simulate a subset of a long trace. Today, this would be done by running a trace splitter offline. The proposal is to support skipping forward N instructions by seeking in the trace file, to make it usable online during simulation.

The records are fixed-size, but the instruction type density is not uniform, so we'd have to do something like embed markers with instruction counts every N records so the seeking can find the proper instruction boundary. We could limit the fast-forward jumps to every N instructions.

There are several features which may not interact well with this feature, where we want to only emit non-changing data once early in the trace and assume a trace reader can cache the data:

• Instruction encodings (#5520) only included for the first dynamic instance of a static instruction, to save space. One solution is to re-emit these at the fast-foward point.

• Physical address translation markers (#4014), which are only emitted on the first instance of a new page (or when mappings change, if that can be detected). Again, a solution would be to re-emit these at the fast-forward "checkpoints".

[derekbruening]

A related feature is having an instruction count in the view tool in addition to the total record count used today, and corresponding -skip_instrs and -sim_instrs to go with today's -skip_refs and -sim_refs (for view and simulator tools).

Also, as part of this feature we should probably solve #4915 / #4948: what about non-fetched instrs?

[derekbruening]

There is a bug in how reader_t is skipping the duplicate top-of-chunk timestamp,cpu header pair: it is assuming single-thread operation and completely fails for serial mode. We saw this in a larger traces with serial mode and it can be reproduced in a small trace where the headers are skipped when there is no chunk:

        8        0: T3 <marker: timestamp 1001>
        9        0: T3 <marker: tid 3 on core 2>
       10        1: T3 ifetch       4 byte(s) @ 0x000000000000002a non-branch
       11        2: T3 ifetch       4 byte(s) @ 0x000000000000002a non-branch
------------------------------------------------------------
       12        3: T7 ifetch       4 byte(s) @ 0x000000000000002a non-branch
       13        4: T7 ifetch       4 byte(s) @ 0x000000000000002a non-branch
------------------------------------------------------------
       14        5: T3 ifetch       4 byte(s) @ 0x000000000000002a non-branch
------------------------------------------------------------
       15        5: T7 <marker: timestamp 1004>
       16        5: T7 <marker: tid 7 on core 3>
       17        6: T7 ifetch       4 byte(s) @ 0x000000000000002a non-branch

[derekbruening]

Split repeating physical address markers as #6654