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DynamoRIO / dynamorio

Dynamic Instrumentation Tool Platform
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Support for realistic TLB size #6232

Open KeeningSunder opened 1 year ago

KeeningSunder commented 1 year ago

When I was trying to simulate a realistic Skylake CPU using Drcachesim, I found that I can not create a TLB with 1536 entries in Drcachesim. Drcachesim only allows TLBs size to be a power of two, which seems like an odd requirement to me, considering that quite a few Intel CPUs in recent years have had non-PO2 TLB sizes.

I would like to use Drcachesim to model my CPU as accurately as possible to better analyze program performance issues. I'd like to know the reason why Drcachesim disallows non-PO2 TLB sizes? Is there workaround to get around it?

https://github.com/DynamoRIO/dynamorio/blob/b420b135b2f394dec44da57cfee290d919f238bb/clients/drcachesim/common/options.cpp#L440-L446

This issue may be related to #4489

derekbruening commented 1 year ago

IIRC @brettcoon updated things to need power-of-2 for size/assoc but not for either individually. Maybe the front-end options for the TLB simulator weren't updated (happy to take a PR for that). If size/assoc isn't enough maybe @brettcoon who was most recently in that code can point to the places where the requirement is needed and what you would have to change to eliminate even that and whether we would want a PR for that.