i#6662 public traces, part 1: synthetic ISA

[edeiana]

A synthetic ISA that has the purpose of preserving register dependencies and giving hints on the type of operation an instruction performs. This PR implements the encoding/decoding functionalities for this new ISA, which we call #DR_ISA_REGDEPS.

Note that being a synthetic ISA, some routines that work on instructions coming from an actual ISA (such as #DR_ISA_AMD64) are not supported (e.g., decode_sizeof()).

Currently we support:

• instr_convert_to_isa_regdeps(): to convert an #instr_t of an actual ISA to a

  DR_ISA_REGDEPS #instr_t.

• instr_encode() and instr_encode_to_copy(): to encode a #DR_ISA_REGDEPS #instr_t into a sequence of contiguous bytes.
• decode() and decode_from_copy(): to decode an encoded #DR_ISA_REGDEPS instruction into an #instr_t.

A #DR_ISA_REGDEPS #instr_t contains the following information:

• categories: composed by #dr_instr_category_t values, they indicate the type of operation performed (e.g., a load, a store, a floating point math operation, a branch, etc.). Note that categories are composable, hence more than one category can be set. This information can be obtained using instr_get_category().
• arithmetic flags: we don't distinguish between different flags, we only report if at least one arithmetic flag was read (all arithmetic flags will be set to read) and/or written (all arithmetic flags will be set to written). This information can be obtained using instr_get_arith_flags().
• number of source and destination operands: we only consider register operands. This information can be obtained using instr_num_srcs() and instr_num_dsts().
• source operation size: is the largest source operand the instruction operates on. This information can be obtained by accessing the #instr_t operation_size field.
• list of register operand identifiers: they are contained in #opnd_t lists, separated in source and destination. Note that these #reg_id_t identifiers are virtual and it should not be assumed that they belong to any DRREG enum value of any specific architecture. These identifiers are meant for tracking register dependencies with respect to other #DR_ISA_REGDEPS instructions only. These lists can be obtained by walking the #instr_t operands with instr_get_dst() and instr_get_src().
• ISA mode: is always #DR_ISA_REGDEPS. This information can be obtained using instr_get_isa_mode().
• encoding bytes: an array of bytes containing the #DR_ISA_REGDEPS #instr_t encoding. Note that this information is present only for decoded instructions (i.e., #instr_t generated by decode() or decode_from_copy()). This information can be obtained using instr_get_raw_bits().
• length: the length of the encoded instruction in bytes. Note that this information is present only for decoded instructions (i.e., #instr_t generated by decode() or decode_from_copy()). This information can be obtained by accessing the #instr_t length field.

Note that all routines that operate on #instr_t and #opnd_t are also supported for

DR_ISA_REGDEPS instructions. However, querying information outside of those

described above (e.g., the instruction opcode with instr_get_opcode()) will return the zeroed value set by instr_create() or instr_init() when the #instr_t was created (e.g., instr_get_opcode() would return OP_INVALID).

[edeiana]

The implementation is somewhat complete, and I believe I addressed all the previous feedback. What's still missing is: 1) What we want to do with https://github.com/DynamoRIO/dynamorio/pull/6691#discussion_r1531686478 (document or change the implementation?) 2) Giant enum for virtual registers. 3) More instructions to test in suite/test/api/ir_x86.c (and perhaps, moving those tests into a new suite/test/api/ir_synthetic.c?). 4) Figure out why suite/test/api/ir_x86.c fails only on windows 32 bit. (<--- figured it out, RAX is a 64-bit register, duh)

[edeiana]

"code_api|tool.drcachesim.invariants" is failing in "ci-x86/x86-64". From the wall of text I get it's hard to understand if it's timing out or actually failing. Will investigate either way using tmate (since I can't reproduce it locally). However, fixing it shouldn't change my work drastically.

Most of the additional work is on collapsing sub-registers into their containing register and adding the register size. This changed the encoding, specifically increasing the operand size from 1 byte to 2 bytes. Also, decoding (and encoding) to/from synthetic ISA is now enabled on all arches. Decoding gets its ISA from dcontext_t, while encoding from instr_t like other ISAs in DR. I added a new suite/test/api/ir_synthetic.c test as well (and removed testing of synthetic ISA from suite/test/api/ir_x86.c) Comments and description have been updated accordingly.

[edeiana]

Ready for review. The main "concern" I have is on the signature of instr_convert_to_isa_regdeps(). Should it be: 1) instr_t* instr_convert_to_isa_regdeps(void *dcontext, instr_t *instr_real_ISA), which calls instr_create() (hence making the user of this function responsible to free the returned instr_regdeps_ISA instruction) (<--- current version) or 2) void instr_convert_to_isa_regdeps(void *dcontext, instr_t *instr_real_ISA, instr_t *instr_regdeps_ISA), where instr_regdeps_ISA is allocated outside. ?