This is the first part of adding RISC-V vector (RVV) extension support to the core.
RVV is a vector architecture similar to SVE, and its vector length (VLEN) can vary from 64 up to 65536. For more information about RVV, please refer to https://github.com/riscv/riscv-isa-manual.
This is the first part of adding RISC-V vector (RVV) extension support to the core.
RVV is a vector architecture similar to SVE, and its vector length (VLEN) can vary from 64 up to 65536. For more information about RVV, please refer to https://github.com/riscv/riscv-isa-manual.
The code itself is compiled and preliminarily tested on real hardware with RVV (VLEN=256) support by running https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/examples/rvv_strlen.c.
isl/v.txt is transformed from https://github.com/riscv/riscv-opcodes/blob/master/rv_v by an off-tree one-time python script.
Follow-up patches will address the following parts with RVV support:
Issue: #3544