”PLATFORM=VerilatedTester make emu“ doesn't work

PGTKi commented 4 years ago

When I execute this command ”PLATFORM=VerilatedTester make emu“, it doesn't work. Erros show as follow: sbt -Dsbt.log.noformat=true "runMain bismo.ChiselMain VerilatedTester /user/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024" /bin/sh: 1: sbt: not found Makefile:122: recipe for target '/user/bismo/build/2x64x2/VerilatedTester/hw/verilog/VerilatedTesterWrapper.v' failed make: *** [/user/bismo/build/2x64x2/VerilatedTester/hw/verilog/VerilatedTesterWrapper.v] Error 127

Besides, two Unit tests pages shown in this link are not found. https://github.com/EECS-NTNU/bismo/blob/master/doc/testing.md

PGTKi commented 4 years ago

sbt not correctly installed.

PGTKi commented 4 years ago

Hello! Anyone would help me? Sadly, when I run "PLATFORM=VerilatedTester make emu" again, I got the following error message. Thanks for any advice in advance.

xs@acalab135:~$ cd bismo/ xs@acalab135:~/bismo$ PLATFORM=VerilatedTester make emu sbt -Dsbt.log.noformat=true "runMain bismo.ChiselMain VerilatedTester /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024" copying runtime jar... [info] [launcher] getting org.scala-sbt sbt 0.13.13 (this may take some time)... downloading https://repo1.maven.org/maven2/org/scala-lang/scala-library/2.10.6/scala-library-2.10.6.jar ... downloading https://repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.0.0-M1/launcher-interface-1.0.0-M1.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo1.maven.org/maven2/org/scala-lang/scala-compiler/2.10.6/scala-compiler-2.10.6.jar ... downloading https://repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.10.6/scala-reflect-2.10.6.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar ... downloading https://repo1.maven.org/maven2/jline/jline/2.13/jline-2.13.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/sbt/0.13.13/jars/sbt.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/relation/0.13.13/jars/relation.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/main-settings/0.13.13/jars/main-settings.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/tasks/0.13.13/jars/tasks.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/completion/0.13.13/jars/completion.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/compiler-ivy-integration/0.13.13/jars/compiler-ivy-integration.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/ivy/0.13.13/jars/ivy.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/logging/0.13.13/jars/logging.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml [SUCCESSFUL ] org.scala-sbt#launcher-interface;1.0.0-M1!launcher-interface.jar (1610ms) downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/run/0.13.13/jars/run.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/compiler-integration/0.13.13/jars/compiler-integration.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/logic/0.13.13/jars/logic.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/command/0.13.13/jars/command.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/task-system/0.13.13/jars/task-system.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/tracking/0.13.13/jars/tracking.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/classpath/0.13.13/jars/classpath.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/interface/0.13.13/jars/interface.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/classfile/0.13.13/jars/classfile.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/process/0.13.13/jars/process.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/control/0.13.13/jars/control.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/compiler-interface/0.13.13/jars/compiler-interface.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/actions/0.13.13/jars/actions.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/testing/0.13.13/jars/testing.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/main/0.13.13/jars/main.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/io/0.13.13/jars/io.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/collections/0.13.13/jars/collections.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml [SUCCESSFUL ] org.fusesource.jansi#jansi;1.11!jansi.jar (2859ms) downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/incremental-compiler/0.13.13/jars/incremental-compiler.jar ... [SUCCESSFUL ] jline#jline;2.13!jline.jar (3385ms) downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/api/0.13.13/jars/api.jar ... :: loading settings :: url = jar:file:/home/xs/.sdkman/candidates/sbt/1.3.13/bin/sbt-launch.jar!/org/apache/ivy/core/settings/ivysettings.xml downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/compile/0.13.13/jars/compile.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/persist/0.13.13/jars/persist.jar ... [SUCCESSFUL ] org.scala-sbt#relation;0.13.13!relation.jar (5947ms) [SUCCESSFUL ] org.scala-sbt#sbt;0.13.13!sbt.jar (6124ms) [SUCCESSFUL ] org.scala-sbt#testing;0.13.13!testing.jar (6316ms) downloading https://repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-2cf13e211b2cb31f0d3b317289dca70eca3362f6/ivy-2.3.0-sbt-2cf13e211b2cb31f0d3b317289dca70eca3362f6.jar ... [SUCCESSFUL ] org.scala-sbt#interface;0.13.13!interface.jar (6943ms) downloading https://repo1.maven.org/maven2/com/jcraft/jsch/0.1.50/jsch-0.1.50.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-tools.sbinary/sbinary_2.10/0.4.2/jars/sbinary_2.10.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/cross/0.13.13/jars/cross.jar ... [SUCCESSFUL ] org.scala-sbt#tracking;0.13.13!tracking.jar (7181ms) downloading https://repo1.maven.org/maven2/org/scala-sbt/serialization_2.10/0.1.2/serialization_2.10-0.1.2.jar ... [SUCCESSFUL ] org.scala-sbt#classfile;0.13.13!classfile.jar (7189ms) downloading https://repo1.maven.org/maven2/org/scala-lang/modules/scala-pickling_2.10/0.10.1/scala-pickling_2.10-0.10.1.jar ... [SUCCESSFUL ] org.scala-sbt#logic;0.13.13!logic.jar (7290ms) downloading https://repo1.maven.org/maven2/org/json4s/json4s-core_2.10/3.2.10/json4s-core_2.10-3.2.10.jar ... [SUCCESSFUL ] org.scala-sbt#control;0.13.13!control.jar (7343ms) downloading https://repo1.maven.org/maven2/org/spire-math/jawn-parser_2.10/0.6.0/jawn-parser_2.10-0.6.0.jar ... [SUCCESSFUL ] org.scala-sbt#process;0.13.13!process.jar (7432ms) downloading https://repo1.maven.org/maven2/org/spire-math/json4s-support_2.10/0.6.0/json4s-support_2.10-0.6.0.jar ... [SUCCESSFUL ] org.scala-sbt#compiler-integration;0.13.13!compiler-integration.jar (7666ms) downloading https://repo1.maven.org/maven2/org/scalamacros/quasiquotes_2.10/2.0.1/quasiquotes_2.10-2.0.1.jar ... [SUCCESSFUL ] org.scala-sbt#tasks;0.13.13!tasks.jar (7667ms) downloading https://repo1.maven.org/maven2/org/json4s/json4s-ast_2.10/3.2.10/json4s-ast_2.10-3.2.10.jar ... [SUCCESSFUL ] org.scala-sbt#run;0.13.13!run.jar (7869ms) downloading https://repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.6/paranamer-2.6.jar ... [SUCCESSFUL ] org.scala-sbt#logging;0.13.13!logging.jar (7940ms) [SUCCESSFUL ] org.scala-sbt#compiler-ivy-integration;0.13.13!compiler-ivy-integration.jar (7990ms) [SUCCESSFUL ] org.scala-sbt#classpath;0.13.13!classpath.jar (8198ms) downloading https://repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar ... [SUCCESSFUL ] org.scala-sbt#persist;0.13.13!persist.jar (5455ms) [SUCCESSFUL ] org.spire-math#json4s-support_2.10;0.6.0!json4s-support_2.10.jar (1548ms) downloading https://repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar ... downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/test-agent/0.13.13/jars/test-agent.jar ... [SUCCESSFUL ] com.jcraft#jsch;0.1.50!jsch.jar (2173ms) downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/cache/0.13.13/jars/cache.jar ... [SUCCESSFUL ] com.thoughtworks.paranamer#paranamer;2.6!paranamer.jar (1852ms) [SUCCESSFUL ] org.spire-math#jawn-parser_2.10;0.6.0!jawn-parser_2.10.jar (2514ms) [SUCCESSFUL ] org.json4s#json4s-ast_2.10;3.2.10!json4s-ast_2.10.jar (2214ms) downloading https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/apply-macro/0.13.13/jars/apply-macro.jar ... [SUCCESSFUL ] org.scala-sbt#completion;0.13.13!completion.jar (9959ms) [SUCCESSFUL ] org.scala-sbt#command;0.13.13!command.jar (9981ms) [SUCCESSFUL ] org.scala-sbt#actions;0.13.13!actions.jar (10018ms) [SUCCESSFUL ] org.scala-sbt#task-system;0.13.13!task-system.jar (10114ms) [SUCCESSFUL ] org.scala-sbt#collections;0.13.13!collections.jar (10282ms) [SUCCESSFUL ] org.scala-sbt#api;0.13.13!api.jar (10401ms) [SUCCESSFUL ] org.scala-sbt#template-resolver;0.1!template-resolver.jar (1673ms) [SUCCESSFUL ] org.scala-sbt#io;0.13.13!io.jar (10690ms) [SUCCESSFUL ] org.scala-sbt#main-settings;0.13.13!main-settings.jar (10717ms) [SUCCESSFUL ] org.scala-sbt#incremental-compiler;0.13.13!incremental-compiler.jar (9119ms) [SUCCESSFUL ] org.scala-sbt#test-interface;1.0!test-interface.jar (2565ms) [SUCCESSFUL ] org.scala-sbt#compile;0.13.13!compile.jar (7879ms) [SUCCESSFUL ] org.scala-sbt#main;0.13.13!main.jar (11677ms) [SUCCESSFUL ] org.scala-tools.sbinary#sbinary_2.10;0.4.2!sbinary_2.10.jar (5898ms) [SUCCESSFUL ] org.scala-sbt#compiler-interface;0.13.13!compiler-interface.jar (12226ms) [SUCCESSFUL ] org.scala-sbt#ivy;0.13.13!ivy.jar (12279ms) [SUCCESSFUL ] org.scala-sbt#cross;0.13.13!cross.jar (6588ms) [SUCCESSFUL ] org.scala-sbt#test-agent;0.13.13!test-agent.jar (5379ms) [SUCCESSFUL ] org.scala-sbt#cache;0.13.13!cache.jar (5621ms) [SUCCESSFUL ] org.scala-sbt#apply-macro;0.13.13!apply-macro.jar (5680ms) [SUCCESSFUL ] org.scala-lang.modules#scala-pickling_2.10;0.10.1!scala-pickling_2.10.jar (10585ms) [SUCCESSFUL ] org.scala-sbt#serialization_2.10;0.1.2!serialization_2.10.jar (10680ms) [SUCCESSFUL ] org.json4s#json4s-core_2.10;3.2.10!json4s-core_2.10.jar (19047ms) [SUCCESSFUL ] org.scala-sbt.ivy#ivy;2.3.0-sbt-2cf13e211b2cb31f0d3b317289dca70eca3362f6!ivy.jar (22791ms) [SUCCESSFUL ] org.scalamacros#quasiquotes_2.10;2.0.1!quasiquotes_2.10.jar (33591ms) [SUCCESSFUL ] org.scala-lang#scala-reflect;2.10.6!scala-reflect.jar (92423ms) [SUCCESSFUL ] org.scala-lang#scala-library;2.10.6!scala-library.jar (279596ms) [SUCCESSFUL ] org.scala-lang#scala-compiler;2.10.6!scala-compiler.jar (467026ms) :: retrieving :: org.scala-sbt#boot-app confs: [default] 50 artifacts copied, 0 already retrieved [info] [launcher] getting Scala 2.10.6 (for sbt)... downloading https://repo1.maven.org/maven2/org/scala-lang/jline/2.10.6/jline-2.10.6.jar ... downloading https://repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.4/jansi-1.4.jar ... [SUCCESSFUL ] org.fusesource.jansi#jansi;1.4!jansi.jar (4045ms) [SUCCESSFUL ] org.scala-lang#jline;2.10.6!jline.jar (4896ms) :: retrieving :: org.scala-sbt#boot-scala confs: [default] 5 artifacts copied, 0 already retrieved [info] Loading project definition from /home/xs/bismo/project WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by sbt.ivyint.ErrorMessageAuthenticator$ (file:/home/xs/.sbt/boot/scala-2.10.6/org.scala-sbt/sbt/0.13.13/ivy-0.13.13.jar) to field java.net.Authenticator.theAuthenticator WARNING: Please consider reporting this to the maintainers of sbt.ivyint.ErrorMessageAuthenticator$ WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release java.lang.NullPointerException at java.base/java.util.regex.Matcher.getTextLength(Matcher.java:1770) at java.base/java.util.regex.Matcher.reset(Matcher.java:416) at java.base/java.util.regex.Matcher.(Matcher.java:253) at java.base/java.util.regex.Pattern.matcher(Pattern.java:1133) at java.base/java.util.regex.Pattern.split(Pattern.java:1261) at java.base/java.util.regex.Pattern.split(Pattern.java:1334) at sbt.IO$.pathSplit(IO.scala:797) at sbt.IO$.parseClasspath(IO.scala:912) at sbt.compiler.CompilerArguments.extClasspath(CompilerArguments.scala:66) at sbt.compiler.MixedAnalyzingCompiler$.withBootclasspath(MixedAnalyzingCompiler.scala:188) at sbt.compiler.MixedAnalyzingCompiler$.searchClasspathAndLookup(MixedAnalyzingCompiler.scala:166) at sbt.compiler.MixedAnalyzingCompiler$.apply(MixedAnalyzingCompiler.scala:176) at sbt.compiler.IC$.incrementalCompile(IncrementalCompiler.scala:138) at sbt.Compiler$.compile(Compiler.scala:155) at sbt.Compiler$.compile(Compiler.scala:141) at sbt.Defaults$.sbt$Defaults$$compileIncrementalTaskImpl(Defaults.scala:879) at sbt.Defaults$$anonfun$compileIncrementalTask$1.apply(Defaults.scala:870) at sbt.Defaults$$anonfun$compileIncrementalTask$1.apply(Defaults.scala:868) at scala.Function1$$anonfun$compose$1.apply(Function1.scala:47) at sbt.$tilde$greater$$anonfun$$u2219$1.apply(TypeFunctions.scala:40) at sbt.std.Transform$$anon$4.work(System.scala:63) at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:228) at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:228) at sbt.ErrorHandling$.wideConvert(ErrorHandling.scala:17) at sbt.Execute.work(Execute.scala:237) at sbt.Execute$$anonfun$submit$1.apply(Execute.scala:228) at sbt.Execute$$anonfun$submit$1.apply(Execute.scala:228) at sbt.ConcurrentRestrictions$$anon$4$$anonfun$1.apply(ConcurrentRestrictions.scala:159) at sbt.CompletionService$$anon$2.call(CompletionService.scala:28) at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515) at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628) at java.base/java.lang.Thread.run(Thread.java:834) [error] (compile:compileIncremental) java.lang.NullPointerException Project loading failed: (r)etry, (q)uit, (l)ast, or (i)gnore? r

PGTKi commented 4 years ago

sbt version not correct. 0.13.13 is needed.

PGTKi commented 4 years ago

However, there is still an error thrown. sbt -Dsbt.log.noformat=true "runMain bismo.ChiselMain VerilatedTester /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024" [info] Loading project definition from /home/xs/bismo/project [info] Set current project to bismo (in build file:/home/xs/bismo/) [info] Running bismo.ChiselMain VerilatedTester /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024 buildInfoPackage: Chisel, version: 2.2.39, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2018-04-18 17:37:17.153, builtAtMillis: 1524073037153 LHS 0 assigned to node# 0 LHS 1 assigned to node# 1 RHS 0 assigned to node# 2 RHS 1 assigned to node# 3 Generating register file mappings... Signal signature mapped to single reg 0 Signal ackqueue_bits mapped to single reg 1 Signal ackqueue_ready mapped to single reg 2 Signal ackqueue_valid mapped to single reg 3 Signal addtoken_ef mapped to single reg 4 Signal addtoken_re mapped to single reg 5 Signal cmdqueue_bits_actualPrecision mapped to single reg 6 Signal cmdqueue_bits_dramBaseAddrDst mapped to single reg 7 Signal cmdqueue_bits_dramBaseAddrSrc mapped to single reg 8 Signal cmdqueue_bits_matrixColsGroup mapped to single reg 9 Signal cmdqueue_bits_matrixRows mapped to single reg 10 Signal cmdqueue_bits_signed mapped to single reg 11 Signal cmdqueue_bits_waitCompleteBytes mapped to single reg 12 Signal cmdqueue_ready mapped to single reg 13 Signal cmdqueue_valid mapped to single reg 14 Signal dsc_bits mapped to regs 15 16 17 18 19 20 21 Signal dsc_ready mapped to single reg 22 Signal dsc_valid mapped to single reg 23 Signal enable mapped to single reg 24 Signal exec_enable mapped to single reg 25 Signal exec_op_count mapped to single reg 26 Signal fetch_enable mapped to single reg 27 Signal fetch_op_count mapped to single reg 28 Signal hw_accWidth mapped to single reg 29 Signal hw_cmdQueueEntries mapped to single reg 30 Signal hw_dpaDimCommon mapped to single reg 31 Signal hw_dpaDimLHS mapped to single reg 32 Signal hw_dpaDimRHS mapped to single reg 33 Signal hw_lhsEntriesPerMem mapped to single reg 34 Signal hw_maxShiftSteps mapped to single reg 35 Signal hw_readChanWidth mapped to single reg 36 Signal hw_rhsEntriesPerMem mapped to single reg 37 Signal hw_writeChanWidth mapped to single reg 38 Signal insOrDsc mapped to single reg 39 Signal ins_bits mapped to regs 40 41 42 43 Signal ins_ready mapped to single reg 44 Signal ins_valid mapped to single reg 45 Signal perf_cc mapped to single reg 46 Signal perf_cc_enable mapped to single reg 47 Signal perf_prf_exec_count mapped to single reg 48 Signal perf_prf_exec_sel mapped to single reg 49 Signal perf_prf_fetch_count mapped to single reg 50 Signal perf_prf_fetch_sel mapped to single reg 51 Signal perf_prf_res_count mapped to single reg 52 Signal perf_prf_res_sel mapped to single reg 53 Signal result_enable mapped to single reg 54 Signal result_op_count mapped to single reg 55 Signal tc_ef mapped to single reg 56 Signal tc_er mapped to single reg 57 Signal tc_fe mapped to single reg 58 Signal tc_re mapped to single reg 59 [info] [0.794] // COMPILING <TesterWrapper (class fpgatidbits.PlatformWrapper.VerilatedTesterWrapper)>(29) [info] [0.963] giving names [info] [1.074] executing custom transforms [info] [1.075] convert masked writes of inline mems [info] [1.119] adding clocks and resets [info] [1.176] inferring widths [info] [1.336] checking widths [info] [1.387] lowering complex nodes to primitives [info] [1.429] removing type nodes [info] [1.501] compiling 12623 nodes [info] [1.502] computing memory ports [info] [1.569] resolving nodes to the components [info] [1.797] creating clock domains [info] [1.822] pruning unconnected IOs [info] [1.828] checking for combinational loops [info] [1.879] NO COMBINATIONAL LOOP FOUND [info] [2.023] COMPILING <RegFile (class fpgatidbits.regfile.RegFile)> 0 CHILDREN (0,1) [info] [2.065] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.068] COMPILING <Queue_1 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.074] 2 components [info] [2.074] COMPILING <Queue_2 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.078] 3 components [info] [2.078] COMPILING <Queue_3 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.082] 4 components [info] [2.082] COMPILING <Queue_4 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.086] 5 components [info] [2.087] COMPILING <Queue_5 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.092] 6 components [info] [2.092] COMPILING <Queue_6 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.096] 7 components [info] [2.096] COMPILING <Queue_7 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.100] 8 components [info] [2.100] COMPILING <Queue_8 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.102] 9 components [info] [2.102] COMPILING <Queue_9 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.104] 10 components [info] [2.104] COMPILING <Queue_10 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.107] 11 components [info] [2.107] COMPILING <Queue_11 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.110] 12 components [info] [2.110] COMPILING <Queue_12 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.113] 13 components [info] [2.113] COMPILING <Queue_13 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.115] 14 components [info] [2.115] COMPILING <Queue_14 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.117] 15 components [info] [2.117] COMPILING <Queue_15 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.118] COMPILING <Queue_16 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.119] COMPILING <Queue_17 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.121] 16 components [info] [2.121] COMPILING <Queue_18 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.123] 17 components [info] [2.123] COMPILING <Queue_19 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.125] 18 components [info] [2.125] COMPILING <Queue_20 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.129] 19 components [info] [2.129] COMPILING <Queue_21 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.131] 20 components [info] [2.132] COMPILING <Queue_22 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.134] 21 components [info] [2.134] COMPILING <Queue_23 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.136] 22 components [info] [2.136] COMPILING <Queue_24 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.137] 23 components [info] [2.137] COMPILING <Queue_25 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.139] 24 components [info] [2.139] COMPILING <Queue_26 (class Chisel.Queue)> 0 CHILDREN (0,1) [info] [2.140] 25 components [info] [2.140] COMPILING <ExecInstrGen (class bismo.ExecInstrGen)> 0 CHILDREN (0,2) [info] [2.141] COMPILING <FetchInstrGen (class bismo.FetchInstrGen)> 0 CHILDREN (0,2) [info] [2.141] COMPILING <ResultInstrGen (class bismo.ResultInstrGen)> 0 CHILDREN (0,2) [info] [2.141] COMPILING <DecoupledInputMux (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.142] COMPILING <DecoupledInputMux_1 (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.142] 2 components [info] [2.142] COMPILING <DecoupledInputMux_2 (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.143] 3 components [info] [2.143] COMPILING <Arbiter (class Chisel.Arbiter)> 0 CHILDREN (0,2) [info] [2.143] COMPILING <Arbiter_1 (class Chisel.Arbiter)> 0 CHILDREN (0,2) [info] [2.144] 2 components [info] [2.144] COMPILING <DecoupledInputMux_3 (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.145] COMPILING <DecoupledInputMux_4 (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.146] 2 components [info] [2.146] COMPILING <DecoupledInputMux_5 (class fpgatidbits.streams.DecoupledInputMux)> 0 CHILDREN (0,2) [info] [2.147] COMPILING <DecoupledOutputDemux (class fpgatidbits.streams.DecoupledOutputDemux)> 0 CHILDREN (0,2) [info] [2.148] COMPILING <DecoupledOutputDemux_1 (class fpgatidbits.streams.DecoupledOutputDemux)> 0 CHILDREN (0,2) [info] [2.149] 2 components [info] [2.149] COMPILING <FetchRouteGen (class bismo.FetchRouteGen)> 0 CHILDREN (0,3) [info] [2.151] COMPILING <FetchInterconnect (class bismo.FetchInterconnect)> 0 CHILDREN (0,3) [info] [2.153] COMPILING <StreamFilter (class fpgatidbits.streams.StreamFilter)> 0 CHILDREN (0,3) [info] [2.153] COMPILING <addrgen_d (class bismo.ExecAddrGen)> 0 CHILDREN (0,3) [info] [2.154] COMPILING <StateProfiler (class fpgatidbits.profiler.StateProfiler)> 0 CHILDREN (0,3) [info] [2.156] COMPILING <StateProfiler (class fpgatidbits.profiler.StateProfiler)> 0 CHILDREN (0,3) [info] [2.158] 2 components [info] [2.158] COMPILING <StateProfiler (class fpgatidbits.profiler.StateProfiler)> 0 CHILDREN (0,3) [info] [2.159] 3 components [info] [2.159] COMPILING <DualPortBRAM_NoBlackBox (class fpgatidbits.ocm.DualPortBRAM_NoBlackBox)> 0 CHILDREN (0,3) [info] [2.160] COMPILING <DualPortBRAM_NoBlackBox (class fpgatidbits.ocm.DualPortBRAM_NoBlackBox)> 0 CHILDREN (0,3) [info] [2.160] 2 components [info] [2.161] COMPILING <DualPortBRAM_NoBlackBox (class fpgatidbits.ocm.DualPortBRAM_NoBlackBox)> 0 CHILDREN (0,3) [info] [2.161] 3 components [info] [2.161] COMPILING <DualPortBRAM_NoBlackBox (class fpgatidbits.ocm.DualPortBRAM_NoBlackBox)> 0 CHILDREN (0,3) [info] [2.161] 4 components [info] [2.162] COMPILING <StreamDeinterleaver (class fpgatidbits.streams.StreamDeinterleaver)> 0 CHILDREN (0,3) [info] [2.163] COMPILING <StreamingSignCorrection (class bismo.StreamingSignCorrection)> 0 CHILDREN (0,3) [info] [2.164] COMPILING <StreamFilter (class fpgatidbits.streams.StreamFilter)> 0 CHILDREN (0,3) [info] [2.164] COMPILING <MultiSeqGen (class bismo.MultiSeqGen)> 0 CHILDREN (0,4) [info] [2.165] COMPILING <BurstyMultiSeqGen (class bismo.BurstyMultiSeqGen)> 0 CHILDREN (0,4) [info] [2.168] COMPILING <MultiSeqGen (class bismo.MultiSeqGen)> 0 CHILDREN (0,4) [info] [2.170] 2 components [info] [2.170] COMPILING <BurstyMultiSeqGen (class bismo.BurstyMultiSeqGen)> 0 CHILDREN (0,4) [info] [2.172] 2 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] 2 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] 3 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] 4 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] 5 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.172] 6 components [info] [2.172] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,4) [info] [2.173] 7 components [info] [2.173] COMPILING <MultiSeqGen (class bismo.MultiSeqGen)> 0 CHILDREN (0,4) [info] [2.174] 3 components [info] [2.174] COMPILING <BurstyMultiSeqGen (class bismo.BurstyMultiSeqGen)> 0 CHILDREN (0,4) [info] [2.176] 3 components [info] [2.176] COMPILING <MultiSeqGen (class bismo.MultiSeqGen)> 0 CHILDREN (0,4) [info] [2.177] 4 components [info] [2.177] COMPILING <BurstyMultiSeqGen (class bismo.BurstyMultiSeqGen)> 0 CHILDREN (0,4) [info] [2.178] 4 components [info] [2.179] COMPILING <Counter (class fpgatidbits.math.Counter)> 0 CHILDREN (0,4) [info] [2.179] COMPILING <Counter_1 (class fpgatidbits.math.Counter)> 0 CHILDREN (0,4) [info] [2.179] 2 components [info] [2.180] COMPILING <SerialInParallelOut (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.181] COMPILING <SerialInParallelOut_1 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.182] 2 components [info] [2.182] COMPILING <SerialInParallelOut_2 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.184] 3 components [info] [2.184] COMPILING <SerialInParallelOut_3 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.185] 4 components [info] [2.185] COMPILING <SerialInParallelOut_4 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.188] 5 components [info] [2.188] COMPILING <SerialInParallelOut_5 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.189] 6 components [info] [2.190] COMPILING <SerialInParallelOut_6 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.191] 7 components [info] [2.191] COMPILING <SerialInParallelOut_7 (class fpgatidbits.streams.SerialInParallelOut)> 0 CHILDREN (0,4) [info] [2.192] 8 components [info] [2.193] COMPILING <compressor (class bismo.BlackBoxCompressorModel)> 0 CHILDREN (0,5) [info] [2.198] COMPILING <compressor (class bismo.BlackBoxCompressorModel)> 0 CHILDREN (0,5) [info] [2.205] 2 components [info] [2.205] COMPILING <compressor (class bismo.BlackBoxCompressorModel)> 0 CHILDREN (0,5) [info] [2.213] 3 components [info] [2.214] COMPILING <compressor (class bismo.BlackBoxCompressorModel)> 0 CHILDREN (0,5) [info] [2.220] 4 components [info] [2.220] COMPILING <shiftReg (class fpgatidbits.streams.ParallelInSerialOut)> 0 CHILDREN (0,5) [info] [2.221] COMPILING <DualPortBRAM (class fpgatidbits.ocm.DualPortBRAM)> 0 CHILDREN (0,5) [info] [2.221] 8 components [info] [2.221] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.222] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.223] 2 components [info] [2.223] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.225] 3 components [info] [2.225] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.227] 4 components [info] [2.227] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.228] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.229] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,5) [info] [2.230] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.231] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.232] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.233] 2 components [info] [2.233] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.234] 3 components [info] [2.235] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.236] 4 components [info] [2.236] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.237] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.238] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,6) [info] [2.239] 2 components [info] [2.239] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.240] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.243] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.245] 2 components [info] [2.246] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.248] 2 components [info] [2.248] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.249] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.251] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.253] 2 components [info] [2.253] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.254] 3 components [info] [2.254] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.255] 3 components [info] [2.255] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.257] 4 components [info] [2.257] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,7) [info] [2.258] 4 components [info] [2.258] COMPILING <Queue (class Chisel.Queue)> 0 CHILDREN (0,8) [info] [2.259] COMPILING <FetchDecoupledController (class bismo.FetchDecoupledController)> 1 CHILDREN (1,2) [info] [2.269] COMPILING <ExecDecoupledController (class bismo.ExecDecoupledController)> 1 CHILDREN (1,2) [info] [2.272] COMPILING <ResultController (class bismo.ResultController)> 1 CHILDREN (1,2) [info] [2.274] COMPILING <PipelinedDualPortBRAM (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,2) [info] [2.275] COMPILING <PipelinedDualPortBRAM_1 (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,2) [info] [2.275] 2 components [info] [2.275] COMPILING <PipelinedDualPortBRAM_2 (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,2) [info] [2.276] 3 components [info] [2.276] COMPILING <PipelinedDualPortBRAM_3 (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,2) [info] [2.276] 4 components [info] [2.277] COMPILING <PipelinedDualPortBRAM (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,3) [info] [2.278] COMPILING <PipelinedDualPortBRAM (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,3) [info] [2.278] 2 components [info] [2.278] COMPILING <PipelinedDualPortBRAM (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,3) [info] [2.279] 3 components [info] [2.279] COMPILING <PipelinedDualPortBRAM (class fpgatidbits.ocm.PipelinedDualPortBRAM)> 1 CHILDREN (1,3) [info] [2.280] 4 components [info] [2.280] COMPILING <P2SKernel_Fast (class bismo.P2SKernel_Fast)> 10 CHILDREN (1,3) [info] [2.287] COMPILING <DotProductUnit (class bismo.DotProductUnit)> 1 CHILDREN (1,4) [info] [2.289] COMPILING <DotProductUnit_1 (class bismo.DotProductUnit)> 1 CHILDREN (1,4) [info] [2.291] 2 components [info] [2.291] COMPILING <DotProductUnit_2 (class bismo.DotProductUnit)> 1 CHILDREN (1,4) [info] [2.293] 3 components [info] [2.293] COMPILING <DotProductUnit_3 (class bismo.DotProductUnit)> 1 CHILDREN (1,4) [info] [2.295] 4 components [info] [2.295] COMPILING <AXIStreamDownsizer (class fpgatidbits.streams.AXIStreamDownsizer)> 1 CHILDREN (1,4) [info] [2.296] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.296] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.296] 2 components [info] [2.296] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.296] 3 components [info] [2.296] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.296] 4 components [info] [2.296] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.296] 5 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.297] 6 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,4) [info] [2.297] 7 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 8 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 9 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 10 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 11 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 12 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 13 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 14 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,5) [info] [2.297] 15 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.297] 16 components [info] [2.297] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 17 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 18 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 19 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 20 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 21 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 22 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 23 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 24 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 25 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,6) [info] [2.298] 26 components [info] [2.298] COMPILING <Q_srl (class fpgatidbits.ocm.Q_srl)> 1 CHILDREN (1,7) [info] [2.298] 27 components [info] [2.298] COMPILING <AsymPipelinedDualPortBRAM (class fpgatidbits.ocm.AsymPipelinedDualPortBRAM)> 1 CHILDREN (2,2) [info] [2.299] COMPILING <AsymPipelinedDualPortBRAM_1 (class fpgatidbits.ocm.AsymPipelinedDualPortBRAM)> 1 CHILDREN (2,2) [info] [2.300] 2 components [info] [2.300] COMPILING <AsymPipelinedDualPortBRAM_2 (class fpgatidbits.ocm.AsymPipelinedDualPortBRAM)> 1 CHILDREN (2,2) [info] [2.300] 3 components [info] [2.301] COMPILING <AsymPipelinedDualPortBRAM_3 (class fpgatidbits.ocm.AsymPipelinedDualPortBRAM)> 1 CHILDREN (2,2) [info] [2.301] 4 components [info] [2.301] COMPILING <DotProductArray (class bismo.DotProductArray)> 4 CHILDREN (2,3) [info] [2.303] COMPILING <StreamResizer (class fpgatidbits.streams.StreamResizer)> 1 CHILDREN (2,3) [info] [2.303] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.304] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.305] 2 components [info] [2.305] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.306] 3 components [info] [2.306] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.307] 4 components [info] [2.307] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.308] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.309] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,3) [info] [2.309] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.310] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.311] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.312] 2 components [info] [2.312] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.313] 3 components [info] [2.313] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.313] 4 components [info] [2.313] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.314] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.315] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,4) [info] [2.315] 2 components [info] [2.315] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.316] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.316] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.317] 2 components [info] [2.317] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.317] 2 components [info] [2.317] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.319] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.321] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.324] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.325] 3 components [info] [2.325] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.326] 3 components [info] [2.326] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.327] 4 components [info] [2.327] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,5) [info] [2.328] 4 components [info] [2.328] COMPILING <SRLQueue (class fpgatidbits.ocm.SRLQueue)> 1 CHILDREN (2,6) [info] [2.328] COMPILING <execStage_direct (class bismo.ExecDecoupledStage)> 2 CHILDREN (3,2) [info] [2.333] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.333] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.333] 2 components [info] [2.334] COMPILING <FPGAQueue_2 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.334] 3 components [info] [2.334] COMPILING <FPGAQueue_3 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.334] 4 components [info] [2.334] COMPILING <FPGAQueue_4 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.335] COMPILING <FPGAQueue_5 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.336] COMPILING <FPGAQueue_6 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,2) [info] [2.336] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.337] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.337] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.338] 2 components [info] [2.338] COMPILING <FPGAQueue_2 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.338] 3 components [info] [2.338] COMPILING <FPGAQueue_3 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.339] 4 components [info] [2.339] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.339] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.340] COMPILING <FPGAQueue_2 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,3) [info] [2.341] 2 components [info] [2.341] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.341] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.342] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.342] 2 components [info] [2.342] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.343] 2 components [info] [2.343] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.345] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.347] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.351] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.351] 3 components [info] [2.351] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.352] 3 components [info] [2.352] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.353] 4 components [info] [2.353] COMPILING <FPGAQueue_1 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,4) [info] [2.353] 4 components [info] [2.353] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (3,5) [info] [2.354] COMPILING <StreamDeinterleaverQueued (class fpgatidbits.streams.StreamDeinterleaverQueued)> 5 CHILDREN (4,2) [info] [2.355] COMPILING <BlockStridedRqGen (class bismo.BlockStridedRqGen)> 4 CHILDREN (4,3) [info] [2.356] COMPILING <BlockStridedRqGen (class bismo.BlockStridedRqGen)> 4 CHILDREN (4,3) [info] [2.357] COMPILING <BRAMQueue (class fpgatidbits.ocm.BRAMQueue)> 2 CHILDREN (4,3) [info] [2.360] COMPILING <BRAMQueue (class fpgatidbits.ocm.BRAMQueue)> 2 CHILDREN (4,3) [info] [2.363] COMPILING <BRAMQueue (class fpgatidbits.ocm.BRAMQueue)> 2 CHILDREN (4,3) [info] [2.367] COMPILING <BlockStridedRqGen (class bismo.BlockStridedRqGen)> 4 CHILDREN (4,3) [info] [2.368] COMPILING <BlockStridedRqGen_1 (class bismo.BlockStridedRqGen)> 4 CHILDREN (4,3) [info] [2.369] COMPILING <BRAMQueue (class fpgatidbits.ocm.BRAMQueue)> 2 CHILDREN (4,4) [info] [2.371] COMPILING <FetchDecoupledStage (class bismo.FetchDecoupledStage)> 5 CHILDREN (5,2) [info] [2.376] COMPILING <FPGAQueue_7 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (5,2) [info] [2.377] COMPILING <FPGAQueue_8 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (5,2) [info] [2.378] COMPILING <FPGAQueue_9 (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (5,2) [info] [2.380] COMPILING <StandAloneP2SAccel (class bismo.StandAloneP2SAccel)> 8 CHILDREN (5,2) [info] [2.386] COMPILING <FPGAQueue (class fpgatidbits.ocm.FPGAQueue)> 1 CHILDREN (5,3) [info] [2.387] COMPILING <ResultStage (class bismo.ResultStage)> 3 CHILDREN (6,2) [info] [2.390] COMPILING <BitSerialMatMulAccel (class bismo.BitSerialMatMulAccel)> 39 CHILDREN (7,1) [info] [2.412] COMPILING <TesterWrapper (class fpgatidbits.PlatformWrapper.VerilatedTesterWrapper)> 29 CHILDREN (8,0) [warn] DecoupledController.scala:159: UNABLE TO FIND probe IN <FetchDecoupledController (class bismo.FetchDecoupledController)> in class bismo.DecoupledController [warn] DecoupledController.scala:159: UNABLE TO FIND probe IN <ExecDecoupledController (class bismo.ExecDecoupledController)> in class bismo.DecoupledController [warn] Controller.scala:137: UNABLE TO FIND probe IN <ResultController (class bismo.ResultController)> in class bismo.BaseController [warn]: Chisel2 is deprecated. Please use Chisel3: https://github.com/freechipsproject/chisel3 [success] Total time: 3 s, completed Sep 7, 2020 12:31:39 PM mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog; \ sbt -Dsbt.log.noformat=true "runMain bismo.HLSMain VerilatedTester 200.0 /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024" [info] Loading project definition from /home/xs/bismo/project [info] Set current project to bismo (in build file:/home/xs/bismo/) [info] Running bismo.HLSMain VerilatedTester 200.0 /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog 2 64 2 1024 1024 buildInfoPackage: Chisel, version: 2.2.39, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2018-04-18 17:37:17.153, builtAtMillis: 1524073037153 LHS 0 assigned to node# 0 LHS 1 assigned to node# 1 RHS 0 assigned to node# 2 RHS 1 assigned to node# 3 Generating HLS dependencies... Generating HLS for ExecAddrGen Writing template defines to /tmp/hls_syn_ExecAddrGen/ExecAddrGen_TemplateDefs.hpp

** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit) SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source /home/xs/Xilinx/Vivado/2019.1/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running '/home/xs/Xilinx/Vivado/2019.1/bin/unwrapped/lnx64.o/vivado_hls' INFO: [HLS 200-10] For user 'xs' on host 'sjtujiangli-PowerEdge-T640' (Linux_x86_64 version 5.4.0-42-generic) on Mon Sep 07 12:31:48 CST 2020 INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS INFO: [HLS 200-10] In directory '/tmp/hls_syn_ExecAddrGen' Sourcing Tcl script '/home/xs/bismo/target/scala-2.11/classes/script/hls_syn.tcl' HLS project: ExecAddrGen HW source file: /home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp Part: xczu3eg-sbva484-1-i Clock period: 5.0 ns Top level function name: ExecAddrGen Include dirs: /home/xs/bismo/target/scala-2.11/classes/cpp/lib /tmp/hls_syn_ExecAddrGen inclDirList: /home/xs/bismo/target/scala-2.11/classes/cpp/lib /tmp/hls_syn_ExecAddrGen includeDirs: -I/home/xs/bismo/target/scala-2.11/classes/cpp/lib -I/tmp/hls_syn_ExecAddrGen INFO: [HLS 200-10] Creating and opening project '/tmp/hls_syn_ExecAddrGen/ExecAddrGen'. INFO: [HLS 200-10] Adding design file '/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp' to the project INFO: [HLS 200-10] Creating and opening solution '/tmp/hls_syn_ExecAddrGen/ExecAddrGen/sol1'. INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-i' INFO: [XFORM 203-1161] The maximum of name length is set into 300. INFO: [SYN 201-201] Setting up clock 'clk' with a period of 5ns. INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [HLS 200-10] Analyzing design file '/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp' ... INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 830.992 ; gain = 128.000 ; free physical = 26029 ; free virtual = 104318 INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 830.992 ; gain = 128.000 ; free physical = 26030 ; free virtual = 104318 INFO: [HLS 200-10] Starting code transformations ... INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 830.992 ; gain = 128.000 ; free physical = 26007 ; free virtual = 104302 INFO: [HLS 200-10] Checking synthesizability ... INFO: [XFORM 203-602] Inlining function 'BISMOExecRunInstruction::fromRaw' into 'ExecAddrGen_Templated<1ul, 16ul, 0ul>' (/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp:102) automatically. INFO: [XFORM 203-602] Inlining function 'ExecAddr::asRaw' into 'ExecAddrGen_Templated<1ul, 16ul, 0ul>' (/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp:116) automatically. INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 830.992 ; gain = 128.000 ; free physical = 25998 ; free virtual = 104295 INFO: [XFORM 203-602] Inlining function 'BISMOExecRunInstruction::fromRaw' into 'ExecAddrGen_Templated<1ul, 16ul, 0ul>' (/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp:102) automatically. INFO: [XFORM 203-602] Inlining function 'ExecAddr::asRaw' into 'ExecAddrGen_Templated<1ul, 16ul, 0ul>' (/home/xs/bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp:116) automatically. INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 830.992 ; gain = 128.000 ; free physical = 25969 ; free virtual = 104266 INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 895.340 ; gain = 192.348 ; free physical = 25957 ; free virtual = 104255 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'ExecAddrGen' ... WARNING: [SYN 201-103] Legalizing function name 'ExecAddrGen_Templated<1ul, 16ul, 0ul>' to 'ExecAddrGen_Templated_1ul_16ul_0ul_s'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ExecAddrGen_Templated_1ul_16ul_0ul_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'Loop 1'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 15.98 seconds; current allocated memory: 127.911 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 128.130 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ExecAddrGen' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 128.176 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.04 seconds; current allocated memory: 128.234 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ExecAddrGen_Templated_1ul_16ul_0ul_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'ExecAddrGen_Templated_1ul_16ul_0ul_s'. INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 128.876 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ExecAddrGen' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'ExecAddrGen/in_V_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'ExecAddrGen/out_V_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on function 'ExecAddrGen' to 'ap_ctrl_none'. INFO: [RTGEN 206-100] Finished creating RTL model for 'ExecAddrGen'. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 129.869 MB. INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 895.340 ; gain = 192.348 ; free physical = 25942 ; free virtual = 104246 INFO: [VHDL 208-304] Generating VHDL RTL for ExecAddrGen. INFO: [VLOG 209-307] Generating Verilog RTL for ExecAddrGen. INFO: [HLS 200-112] Total elapsed time: 16.96 seconds; peak allocated memory: 129.869 MB. INFO: [Common 17-206] Exiting vivado_hls at Mon Sep 7 12:32:04 2020... Generating HLS for ExecInstrGen Writing template defines to /tmp/hls_syn_ExecInstrGen/ExecInstrGen_TemplateDefs.hpp

** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit) SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source /home/xs/Xilinx/Vivado/2019.1/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running '/home/xs/Xilinx/Vivado/2019.1/bin/unwrapped/lnx64.o/vivado_hls' INFO: [HLS 200-10] For user 'xs' on host 'sjtujiangli-PowerEdge-T640' (Linux_x86_64 version 5.4.0-42-generic) on Mon Sep 07 12:32:07 CST 2020 INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS INFO: [HLS 200-10] In directory '/tmp/hls_syn_ExecInstrGen' Sourcing Tcl script '/home/xs/bismo/target/scala-2.11/classes/script/hls_syn.tcl' HLS project: ExecInstrGen HW source file: /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp Part: xczu3eg-sbva484-1-i Clock period: 5.0 ns Top level function name: ExecInstrGen Include dirs: /home/xs/bismo/target/scala-2.11/classes/cpp/lib /tmp/hls_syn_ExecInstrGen inclDirList: /home/xs/bismo/target/scala-2.11/classes/cpp/lib /tmp/hls_syn_ExecInstrGen includeDirs: -I/home/xs/bismo/target/scala-2.11/classes/cpp/lib -I/tmp/hls_syn_ExecInstrGen INFO: [HLS 200-10] Creating and opening project '/tmp/hls_syn_ExecInstrGen/ExecInstrGen'. INFO: [HLS 200-10] Adding design file '/home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp' to the project INFO: [HLS 200-10] Creating and opening solution '/tmp/hls_syn_ExecInstrGen/ExecInstrGen/sol1'. INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-i' INFO: [XFORM 203-1161] The maximum of name length is set into 300. INFO: [SYN 201-201] Setting up clock 'clk' with a period of 5ns. INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [HLS 200-10] Analyzing design file '/home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp' ... ERROR: [HLS 200-70] Compilation errors found: In file included from /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:1: /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:40:3: error: unknown type name 'size_t' size_t LMEM, size_t RMEM, ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:40:16: error: unknown type name 'size_t' size_t LMEM, size_t RMEM, ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:42:3: error: unknown type name 'size_t' size_t ETF_S ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:67:9: error: unknown type name 'size_t' const size_t total_iters = ins_in.tiles_m ins_in.tiles_n ins_in.bits_l * ins_in.bits_r; ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:87:7: error: use of undeclared identifier 'size_t'; did you mean 'sizeof'? for(size_t i = 0; i < total_iters; i++) { ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:87:21: error: use of undeclared identifier 'i' for(size_t i = 0; i < total_iters; i++) { ^ /home/xs/bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp:87:38: error: use of undeclared identifier 'i' for(size_t i = 0; i < total_iters; i++) { ^ 7 errors generated. Failed during preprocessing. while executing "source /home/xs/bismo/target/scala-2.11/classes/script/hls_syn.tcl" ("uplevel" body line 1) invoked from within "uplevel #0 [list source $arg] "

INFO: [Common 17-206] Exiting vivado_hls at Mon Sep 7 12:32:12 2020... cp: cannot stat '/tmp/hls_syn_ExecInstrGen/ExecInstrGen/sol1/impl/verilog/.': No such file or directory [error] (run-main-0) java.lang.RuntimeException: Nonzero exit value: 1 java.lang.RuntimeException: Nonzero exit value: 1 at scala.sys.package$.error(package.scala:27) at scala.sys.process.ProcessBuilderImpl$AbstractBuilder.slurp(ProcessBuilderImpl.scala:132) at scala.sys.process.ProcessBuilderImpl$AbstractBuilder.$bang$bang(ProcessBuilderImpl.scala:102) at fpgatidbits.hlstools.TidbitsHLSTools$.hlsToVerilog(HLSTools.scala:32) at fpgatidbits.TidbitsMakeUtils$$anonfun$makeHLSDependencies$1.apply(Main.scala:149) at fpgatidbits.TidbitsMakeUtils$$anonfun$makeHLSDependencies$1.apply(Main.scala:137) at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) at fpgatidbits.TidbitsMakeUtils$.makeHLSDependencies(Main.scala:137) at bismo.Settings$.makeHLSDependencies(Main.scala:83) at bismo.HLSMain$.main(Main.scala:135) at bismo.HLSMain.main(Main.scala) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) at java.lang.reflect.Method.invoke(Method.java:498) [trace] Stack trace suppressed: run 'last compile:runMain' for the full output. java.lang.RuntimeException: Nonzero exit code: 1 at scala.sys.package$.error(package.scala:27) [trace] Stack trace suppressed: run 'last compile:runMain' for the full output. [error] (compile:runMain) Nonzero exit code: 1 [error] Total time: 29 s, completed Sep 7, 2020 12:32:12 PM Makefile:127: recipe for target '/home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog/ExecInstrGen.v' failed make: *** [/home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog/ExecInstrGen.v] Error 1

PGTKi commented 4 years ago

I add #include <stddef.h> to these files:

bismo/target/scala-2.11/classes/hls/ExecAddrGen.cpp bismo/target/scala-2.11/classes/hls/ExecInstrGen.cpp bismo/target/scala-2.11/classes/hls/FetchInstrGen.cpp bismo/target/scala-2.11/classes/hls/ResultInstrGen.cpp

The error above disappeard.

But, another error shows:

[info] [2.842] COMPILING <TesterWrapper (class fpgatidbits.PlatformWrapper.VerilatedTesterWrapper)> 29 CHILDREN (8,0) [warn] DecoupledController.scala:159: UNABLE TO FIND probe IN <FetchDecoupledController (class bismo.FetchDecoupledController)> in class bismo.DecoupledController [warn] DecoupledController.scala:159: UNABLE TO FIND probe IN <ExecDecoupledController (class bismo.ExecDecoupledController)> in class bismo.DecoupledController [warn] Controller.scala:137: UNABLE TO FIND probe IN <ResultController (class bismo.ResultController)> in class bismo.BaseController [warn]: Chisel2 is deprecated. Please use Chisel3: https://github.com/freechipsproject/chisel3 [success] Total time: 5 s, completed Sep 7, 2020 2:34:52 PM mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \ cp -rf /home/xs/bismo/build/2x64x2/VerilatedTester/hw/verilog/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \ cp -rf /home/xs/bismo/fpga-tidbits/src/main/resources/verilog/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \ cd /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \ verilator -Iother-verilog --cc TesterWrapper.v -Wno-assignin -Wno-fatal -Wno-lint -Wno-style -Wno-COMBDLY -Wno-STMTDLY --Mdir verilated --trace; \ cp -rf /usr/share/verilator/include/verilated.cpp /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog/verilated; \ cp -rf /usr/share/verilator/include/verilated_vcd_c.cpp /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/verilog/verilated; %Error: TesterWrapper.v:9172: Cannot find file containing module: FetchInstrGen %Error: TesterWrapper.v:9172: Looked in: %Error: TesterWrapper.v:9172: other-verilog/FetchInstrGen %Error: TesterWrapper.v:9172: other-verilog/FetchInstrGen.v %Error: TesterWrapper.v:9172: other-verilog/FetchInstrGen.sv %Error: TesterWrapper.v:9172: FetchInstrGen %Error: TesterWrapper.v:9172: FetchInstrGen.v %Error: TesterWrapper.v:9172: FetchInstrGen.sv %Error: TesterWrapper.v:9172: verilated/FetchInstrGen %Error: TesterWrapper.v:9172: verilated/FetchInstrGen.v %Error: TesterWrapper.v:9172: verilated/FetchInstrGen.sv %Error: TesterWrapper.v:9181: Cannot find file containing module: ResultInstrGen %Error: Exiting due to 12 error(s) %Error: Command Failed /usr/bin/verilator_bin -Iother-verilog --cc TesterWrapper.v -Wno-assignin -Wno-fatal -Wno-lint -Wno-style -Wno-COMBDLY -Wno-STMTDLY --Mdir verilated --trace mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy; \ mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/driver; \ mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/test; \ mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/rtlib; \ mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/hls_include; \ cp -rf /home/xs/bismo/build/2x64x2/VerilatedTester/hw/driver/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/driver/; \ cp -rf /home/xs/bismo/src/main/resources/cpp/app/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/test/; cp -rf /home/xs/bismo/src/main/resources/cpp/lib/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/rtlib; \ cp -rf /home/xs/Xilinx/Vivado/2019.1/bin/../include/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/hls_include; mkdir -p /home/xs/bismo/build/2x64x2/VerilatedTester/deploy; cp -f /home/xs/bismo/src/main/script/VerilatedTester/target/ /home/xs/bismo/build/2x64x2/VerilatedTester/deploy/ cd /home/xs/bismo/build/2x64x2/VerilatedTester/deploy; \ sh compile_rtlib.sh; g++: error: verilog/verilated/.cpp: Not a directory platforms/VerilatedTester.mk:63: recipe for target '/home/xs/bismo/build/2x64x2/VerilatedTester/deploy/libbismo_rt.so' failed make: *** [/home/xs/bismo/build/2x64x2/VerilatedTester/deploy/libbismo_rt.so] Error 1

Full Output

PGTKi commented 4 years ago

Here are my setup information: verilator --version Verilator 3.916 2017-11-25 rev verilator_3_914-65-g0478dbd vivado -version Vivado v2019.1 (64-bit) SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

git clone --recurse-submodules https://github.com/EECS-NTNU/bismo.git

Ubuntu 18.04.5 LTS (GNU/Linux 5.4.0-42-generic x86_64)

Alought PLATFORM=VerilatedTester make emu gives error above, it seems make all run successfully.

=======> Driver written to BitSerialMatMulAccel.hpp [success] Total time: 2 s, completed Sep 7, 2020 1:21:41 PM mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy; \ mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy/driver; \ mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy/test; \ mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy/rtlib; \ mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy/hls_include; \ cp -rf /home/xs/bismo/build/2x64x2/PYNQU96/hw/driver/ /home/xs/bismo/build/2x64x2/PYNQU96/deploy/driver/; \ cp -rf /home/xs/bismo/src/main/resources/cpp/app/ /home/xs/bismo/build/2x64x2/PYNQU96/deploy/test/; cp -rf /home/xs/bismo/src/main/resources/cpp/lib/ /home/xs/bismo/build/2x64x2/PYNQU96/deploy/rtlib; \ cp -rf /home/xs/Xilinx/Vivado/2019.1/bin/../include/ /home/xs/bismo/build/2x64x2/PYNQU96/deploy/hls_include; mkdir -p /home/xs/bismo/build/2x64x2/PYNQU96/deploy; cp -f /home/xs/bismo/src/main/script/PYNQU96/target/* /home/xs/bismo/build/2x64x2/PYNQU96/deploy/

EECS-NTNU / bismo

”PLATFORM=VerilatedTester make emu“ doesn't work #10