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EECS-NTNU / bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
BSD 3-Clause "New" or "Revised" License
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”PLATFORM=VerilatedTester make emu“ doesn't work #11

Closed mhgholamrezaei closed 2 years ago

mhgholamrezaei commented 2 years ago

Hello, I tried to run platform emulation. I have the following versions of the requirements: Sbt => 0.13.13 Verilator => 3.916 Vivado and Vivado HLS => 2019.2

And my OS is Ubuntu 20.04.3 LTS.

After running PLATFORM=VerilatedTester make emu, I get the following Errors:(I just posted the tail of the message because it was long)

INFO: [HLS 200-112] Total elapsed time: 15.07 seconds; peak allocated memory: 140.136 MB.
INFO: [Common 17-206] Exiting vivado_hls at Tue Jul  5 11:06:16 2022...
[success] Total time: 69 s, completed Jul 5, 2022 11:06:17 AM
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \
cp -rf /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/hw/verilog/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \
cp -rf /home/zynq-user/worktable/bismo/fpga-tidbits/src/main/resources/verilog/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \
cd /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog; \
verilator -Iother-verilog --cc TesterWrapper.v -Wno-assignin -Wno-fatal -Wno-lint -Wno-style -Wno-COMBDLY -Wno-STMTDLY --Mdir verilated --trace; \
cp -rf /usr/share/verilator/include/verilated.cpp /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog/verilated; \
cp -rf /usr/share/verilator/include/verilated_vcd_c.cpp /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/verilog/verilated;
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120: Cannot find file containing module: regslice_both
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120: Looked in:
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       other-verilog/regslice_both
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       other-verilog/regslice_both.v
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       other-verilog/regslice_both.sv
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       regslice_both
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       regslice_both.v
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       regslice_both.sv
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       verilated/regslice_both
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       verilated/regslice_both.v
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:120:       verilated/regslice_both.sv
%Error: ExecAddrGen_Templated_1ul_16ul_0ul_s.v:134: Cannot find file containing module: regslice_both
%Error: ResultInstrGen_RHSTiling_Templated_2ul_2ul_32ul_s.v:165: Cannot find file containing module: regslice_both
%Error: ResultInstrGen_RHSTiling_Templated_2ul_2ul_32ul_s.v:179: Cannot find file containing module: regslice_both
%Error: FetchInstrGen_RHSLHSTiling_Templated_2ul_64ul_2ul_0ul_1024ul_1024ul_s.v:261: Cannot find file containing module: regslice_both
%Error: FetchInstrGen_RHSLHSTiling_Templated_2ul_64ul_2ul_0ul_1024ul_1024ul_s.v:275: Cannot find file containing module: regslice_both
%Error: ExecInstrGen_RHSLHSTiling_1024ul_1024ul_0ul_s.v:500: Cannot find file containing module: regslice_both
%Error: ExecInstrGen_RHSLHSTiling_1024ul_1024ul_0ul_s.v:514: Cannot find file containing module: regslice_both
%Error: ExecAddrGen.v:86: Cannot find file containing module: regslice_both
%Error: ExecAddrGen.v:100: Cannot find file containing module: regslice_both
%Error: ResultInstrGen.v:86: Cannot find file containing module: regslice_both
%Error: ResultInstrGen.v:100: Cannot find file containing module: regslice_both
%Error: FetchInstrGen.v:86: Cannot find file containing module: regslice_both
%Error: FetchInstrGen.v:100: Cannot find file containing module: regslice_both
%Error: ExecInstrGen.v:86: Cannot find file containing module: regslice_both
%Error: ExecInstrGen.v:100: Cannot find file containing module: regslice_both
%Error: Exiting due to 26 error(s)
%Error: Command Failed /usr/bin/verilator_bin -Iother-verilog --cc TesterWrapper.v -Wno-assignin -Wno-fatal -Wno-lint -Wno-style -Wno-COMBDLY -Wno-STMTDLY --Mdir verilated --trace
mkdir -p "/home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/hw/driver"
sbt -Dsbt.log.noformat=true "runMain bismo.DriverMain VerilatedTester /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/hw/driver /home/zynq-user/worktable/bismo/fpga-tidbits/src/main/resources/cpp/platform-wrapper-regdriver"
[ERROR] Failed to construct terminal; falling back to unsupported
java.lang.NumberFormatException: For input string: "0x100"
    at java.lang.NumberFormatException.forInputString(NumberFormatException.java:65)
    at java.lang.Integer.parseInt(Integer.java:580)
    at java.lang.Integer.valueOf(Integer.java:766)
    at jline.internal.InfoCmp.parseInfoCmp(InfoCmp.java:59)
    at jline.UnixTerminal.parseInfoCmp(UnixTerminal.java:233)
    at jline.UnixTerminal.<init>(UnixTerminal.java:64)
    at jline.UnixTerminal.<init>(UnixTerminal.java:49)
    at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
    at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
    at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
    at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
    at java.lang.Class.newInstance(Class.java:442)
    at jline.TerminalFactory.getFlavor(TerminalFactory.java:209)
    at jline.TerminalFactory.create(TerminalFactory.java:100)
    at jline.TerminalFactory.get(TerminalFactory.java:184)
    at jline.TerminalFactory.get(TerminalFactory.java:190)
    at sbt.ConsoleLogger$.ansiSupported(ConsoleLogger.scala:123)
    at sbt.ConsoleLogger$.<init>(ConsoleLogger.scala:117)
    at sbt.ConsoleLogger$.<clinit>(ConsoleLogger.scala)
    at sbt.GlobalLogging$.initial(GlobalLogging.scala:43)
    at sbt.StandardMain$.initialGlobalLogging(Main.scala:64)
    at sbt.StandardMain$.initialState(Main.scala:73)
    at sbt.xMain.run(Main.scala:29)
    at xsbt.boot.Launch$$anonfun$run$1.apply(Launch.scala:109)
    at xsbt.boot.Launch$.withContextLoader(Launch.scala:128)
    at xsbt.boot.Launch$.run(Launch.scala:109)
    at xsbt.boot.Launch$$anonfun$apply$1.apply(Launch.scala:35)
    at xsbt.boot.Launch$.launch(Launch.scala:117)
    at xsbt.boot.Launch$.apply(Launch.scala:18)
    at xsbt.boot.Boot$.runImpl(Boot.scala:41)
    at xsbt.boot.Boot$.main(Boot.scala:17)
    at xsbt.boot.Boot.main(Boot.scala)

[info] Loading project definition from /home/zynq-user/worktable/bismo/project
[info] Set current project to bismo (in build file:/home/zynq-user/worktable/bismo/)
[info] Running bismo.DriverMain VerilatedTester /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/hw/driver /home/zynq-user/worktable/bismo/fpga-tidbits/src/main/resources/cpp/platform-wrapper-regdriver
buildInfoPackage: Chisel, version: 2.2.39, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2018-04-18 17:37:17.153, builtAtMillis: 1524073037153
LHS 0 assigned to node# 0
LHS 1 assigned to node# 1
RHS 0 assigned to node# 2
RHS 1 assigned to node# 3
Generating register file mappings...
Signal signature mapped to single reg 0
Signal ackqueue_bits mapped to single reg 1
Signal ackqueue_ready mapped to single reg 2
Signal ackqueue_valid mapped to single reg 3
Signal addtoken_ef mapped to single reg 4
Signal addtoken_re mapped to single reg 5
Signal cmdqueue_bits_actualPrecision mapped to single reg 6
Signal cmdqueue_bits_dramBaseAddrDst mapped to single reg 7
Signal cmdqueue_bits_dramBaseAddrSrc mapped to single reg 8
Signal cmdqueue_bits_matrixColsGroup mapped to single reg 9
Signal cmdqueue_bits_matrixRows mapped to single reg 10
Signal cmdqueue_bits_signed mapped to single reg 11
Signal cmdqueue_bits_waitCompleteBytes mapped to single reg 12
Signal cmdqueue_ready mapped to single reg 13
Signal cmdqueue_valid mapped to single reg 14
Signal dsc_bits mapped to regs 15 16 17 18 19 20 21
Signal dsc_ready mapped to single reg 22
Signal dsc_valid mapped to single reg 23
Signal enable mapped to single reg 24
Signal exec_enable mapped to single reg 25
Signal exec_op_count mapped to single reg 26
Signal fetch_enable mapped to single reg 27
Signal fetch_op_count mapped to single reg 28
Signal hw_accWidth mapped to single reg 29
Signal hw_cmdQueueEntries mapped to single reg 30
Signal hw_dpaDimCommon mapped to single reg 31
Signal hw_dpaDimLHS mapped to single reg 32
Signal hw_dpaDimRHS mapped to single reg 33
Signal hw_lhsEntriesPerMem mapped to single reg 34
Signal hw_maxShiftSteps mapped to single reg 35
Signal hw_readChanWidth mapped to single reg 36
Signal hw_rhsEntriesPerMem mapped to single reg 37
Signal hw_writeChanWidth mapped to single reg 38
Signal insOrDsc mapped to single reg 39
Signal ins_bits mapped to regs 40 41 42 43
Signal ins_ready mapped to single reg 44
Signal ins_valid mapped to single reg 45
Signal perf_cc mapped to single reg 46
Signal perf_cc_enable mapped to single reg 47
Signal perf_prf_exec_count mapped to single reg 48
Signal perf_prf_exec_sel mapped to single reg 49
Signal perf_prf_fetch_count mapped to single reg 50
Signal perf_prf_fetch_sel mapped to single reg 51
Signal perf_prf_res_count mapped to single reg 52
Signal perf_prf_res_sel mapped to single reg 53
Signal result_enable mapped to single reg 54
Signal result_op_count mapped to single reg 55
Signal tc_ef mapped to single reg 56
Signal tc_er mapped to single reg 57
Signal tc_fe mapped to single reg 58
Signal tc_re mapped to single reg 59
dsc_bits is split across more than 2 regs, write manually
ins_bits is split across more than 2 regs, write manually
=======> Driver written to BitSerialMatMulAccel.hpp
[success] Total time: 1 s, completed Jul 5, 2022 11:06:21 AM
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy; \
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/driver; \
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/test; \
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/rtlib; \
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/hls_include; \
cp -rf /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/hw/driver/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/driver/; \
cp -rf /home/zynq-user/worktable/bismo/src/main/resources/cpp/app/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/test/;
cp -rf /home/zynq-user/worktable/bismo/src/main/resources/cpp/lib/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/rtlib; \
cp -rf /home/zynq-user/xilinx/2019.2/Vivado/2019.2/bin/../include/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/hls_include;
mkdir -p /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy; cp -f /home/zynq-user/worktable/bismo/src/main/script/VerilatedTester/target/* /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/
cd /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy; \
sh compile_rtlib.sh;
g++: error: verilog/verilated/*.cpp: Not a directory
make: *** [platforms/VerilatedTester.mk:63: /home/zynq-user/worktable/bismo/build/2x64x2/VerilatedTester/deploy/libbismo_rt.so] Error 1

Is there any problem with my Verilator version?

mhgholamrezaei commented 2 years ago

I built Verilator (version 3.916) from its source code and installed Vivado 2018.3. Now, the problem is gone.