EPFL-LAP / dynamatic

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
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[LSQ] Deadlocking State Involving lsq_load, end_signal, and data_from_lsq #135

Open Jiahui17 opened 2 months ago

Jiahui17 commented 2 months ago

Benchmark:

while_loop_2.c

Commit:

commit de10cdfa05bfc02e1de7f420b8776548936758a6 (official/main)
Author: Lucas Ramirez <lucas.rami@proton.me>
Date:   Thu Aug 29 18:42:33 2024 +0200

    [Handshake] Fix incorrect mem. iface. port identifiation

To reproduce the bug, use the following script:

dynamatic> set-dynamatic-path ./dynamatic;   set-src ./dynamatic/integration-test/while_loop_2/while_loop_2.c;   set-clock-period 4;   compile  ;   write-hdl --hdl vhdl;   simulate; #  synthesize;   exit

Possible cause:

deadlock_cycle

Possible cyclic dependency (see the figure above):

Thus, the circuit deadlocks.

One obvious mistake here is that the wrong fork produces the end signal (notice that the normal fork below the lazy fork only has one output.