EPFL-LAP / dynamatic

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
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[Speculation] Ready bit of the speculator's signals are always 1, causing bug when predecessor stalls #173

Open shundroid opened 1 month ago

shundroid commented 1 month ago

Background: The speculator receives two inputs. One is the (real) data, which is used for the comparison with the predicted data (sometimes also speculative data). The other is a control token called enable signal, which is used to determine the timing of performing speculation.

In Haoran's implementation, the two ready bits of the predictor (internal module in the speculator) are always set to 1, which makes the speculator's all ready signals always 1. It may cause a bug in the following situation.

In the circuit of the figure below, when the data channel of the cond_br stalls, the output data of the speculator also stalls. If the two inputs of the speculator don't stall, it loses some tokens that should be passed to predecessor units and causes the matching problem.

image

shundroid commented 1 month ago

To fix this, I made the predictor's ready bits depend on the ready signal from the internal predecessor unit. image

Note that the predictor is connected to the speculator's inputs like this way: image

Fixed in #172