This PR adds support for the basic floating-point arithmetic units in the experimental backend. This PR largely reused the changes made in #76, which uses flopoco-generated IP cores to replace the proprietary IP cores extracted from Vivado HLS.
Changes:
Flopoco-generated IPs are copied to the experimental RTL library.
addf, subf, mulf, divf, cmpf now use the flopoco-generated IP cores.
cmpf is now based on a more verbose opcode (cmpf-generator is also updated).
Dependency update in rtl-config.json
All the VHDL floating-point units now explicitly assert if operating on 32-bit data.
New benchmarks (integration-test) that use floating-point units.
Future work:
Characterization of flopoco-generated units
Flexible bit-width or number format
Bonus change:
CMake configuration flags are now added into .vscode/settings.json (those flags are identical to the ones in build.sh)
Known issues:
Some new benchmarks are not working with the experimental backend.
This PR adds support for the basic floating-point arithmetic units in the experimental backend. This PR largely reused the changes made in #76, which uses flopoco-generated IP cores to replace the proprietary IP cores extracted from Vivado HLS.
Changes:
addf
,subf
,mulf
,divf
,cmpf
now use the flopoco-generated IP cores.cmpf
is now based on a more verbose opcode (cmpf-generator
is also updated).rtl-config.json
Future work:
Bonus change:
.vscode/settings.json
(those flags are identical to the ones inbuild.sh
)Known issues: