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ERC-IIITH / Verilog-Library

Comprehensive hardware library in Verilog for hardware primitives
MIT License
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Gates #5

Open adithyasunil26 opened 3 years ago

adithyasunil26 commented 3 years ago

2 input AND, OR, NAND, NOR, XOR and XNOR gates and NOT gate RTL model using operators and structural model using gate primitives

File structure example

nand

nand_struct.v nand_struct_tb.v nand_rtl.v nand_rtl_tb.v

where _struct is for the structural model and _rtl for the RTL model

This issue can be broken down and solved in multiple PRs.

KarthikL1729 commented 3 years ago

Can I take this up? I'll take the XOR gate?

adithyasunil26 commented 3 years ago

@KarthikL1729 Sure. Go ahead.

challatharun commented 3 years ago

can i take AND,OR gates? @adithyasunil26

The-Endurance commented 2 years ago

Can I take NAND?

adithyasunil26 commented 2 years ago

@The-Endurance Yep. Go ahead.

164adityakumar commented 1 year ago

Can i please take up XNOR gate?