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ERC-IIITH / Verilog-Library

Comprehensive hardware library in Verilog for hardware primitives
MIT License
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D-Flipflop #6

Closed adithyasunil26 closed 2 years ago

adithyasunil26 commented 3 years ago

RTL model using always block and structural model using gate modules from #5.

File structure example

d_ff

d_ff_struct.v d_ff_struct_tb.v d_ff.v d_ff_tb.v

where _struct is for the structural model and no suffix for the RTL model

This issue can be broken down and solved in multiple PRs for the structural and RTL models respectively.

Siddharth1002 commented 3 years ago

I would like to work on this issue. Can u please assign this to me?

adithyasunil26 commented 3 years ago

@Siddharth1002 Yep. Go ahead.

Siddharth1002 commented 3 years ago

Submitted the pull request. Please have a look

The-Endurance commented 2 years ago

Is this done? If not, can I take it up?

adithyasunil26 commented 2 years ago

@The-Endurance You can take it up. Re-assigning the issue to you.